S5PV210 Development Series One _ development environment and startup mode

S5PV210 Development Series One development environment and startup mode

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The arm core is widely used in various fields, including ARM7, ARM9, ARM11, Cortex-m, and Cortex-a, for its high performance, low power consumption and low cost. Many semiconductor vendors such as NXP, Freescale, Atmel, Samsung, TI, etc. have designed their own general-purpose processors based on arm cores, from low-cost control processors to high-performance application processors that have gone deep into every aspect of our lives. The author provides a brief introduction to Samsung's CORTEX-A8 processor s5pv210.

1. S5PV210 Overview

The s5pv210 is a low-power, low-cost, high-performance mobile and general-application micro-processing solution that integrates with the ARMV7 architecture-based CORTEX-A8 core to support a wide range of peripherals.

The s5pv210 incorporates a 64-bit internal bus architecture and includes many powerful acceleration hardware, for example, for graphics, image acceleration, display, and scaling cropping. The Integrated Multimedia format encoding (MFC) supports codec MPEG-1/2/4, H.263, and H, and also supports real-time conferencing, Analog TV output, HD video, pal, and more.

The key features of the s5pv210 are as follows:

• ARM Cortex-a8 core with neon signal processing extension, 32/32k instruction/data cache and 512k level two cache, frequency [email protected]
• 64-bit Multilayer bus architecture
• Advanced Power Management System
• On-chip 64k ROM and 128k RAM for secure boot
• 8-bit ITU 601/656 camera interface with a lateral maximum of 4224 pixels (telescoping) or 8192 pixels (non-retractable)
• Multi-format codec unit support mpeg-4/h.263/h.264 codec, maximum support [email protected], support MPEG2/VC1/DIVX decoding, maximum support [email protected]
• JPEG codec support 80 million pixels per second
• Support 3D/2D Multimedia acceleration
• 1/2/4/8 Palette or 8/16/24-bit non-palette TFT controller
• Supports analog TV signal output and HD video interface
• Support MIPI-DSI and MIPI-CSI
• 1-Way AC97 Audio codec interface and 3-channel PCM serial Port audio interface
• 3-Channel 24-bit I2S interface
• 1-way single output S/PDIF Digital audio interface
• 3-Channel I²c interface
• 2-Channel SPI interface
• 4-channel UART interface with Bluetooth 2.0 support
• 1 x USB 2.0 OTG Controller
• 1 x USB 2.0 host Controller
• Supports asynchronous modem interfaces
• 4-Channel SD/SDIO/HS-MMC interface
• Supports ATA/ATAPI-6 standard interface
• 24-Channel Dam control
• Support 14x8 Matrix keyboard
• 10-Channel 12-bit multiplexed ADC
• Configurable Gpio ports
• Real-time clock, PLL, timer, watchdog, etc.
• system clock for accurate timekeeping in power-down mode
• Support for expandable memory interfaces

2. S5PV210 Development Environment 2.1. Instruction Set

S5PV210 is the Cortex-a8 kernel, which is a armv7-a architecture that supports two primary instruction sets: 32-bit ARM instruction set and 16/32-bit Thumb-2 instruction set. The arm instruction set has a 32-bit length for each instruction, has the highest efficiency, but also requires more code space, the arm instruction set is backwards compatible, that is, the ARMV7-A processor can directly execute the ARMV4 architecture's arm instruction set code (such as ARM7 's application code). Thumb-2 is the extended instruction set of the thumb, before the ARMv6 architecture, the thumb as a 16-bit instruction set, as a subset of the arm instruction set, it is proposed to reduce the amount of code, is not complete, only support the general function, unable to detach from the arm instruction set. In the ARMV7 architecture, Thumb-2, as a prerequisite instruction set, supports the 16/32 hybrid instruction pattern, virtually all arm instruction set functionality, and is nearly as efficient as the arm instruction set, and the code density is close to the Thumb instruction set. The introduction of the Thumb-2 instruction set means that the program memory can be smaller, in some cache applications, the same capacity instruction cache can cache more instructions, improve the command cache hit rate, and indirectly improve the kernel performance. For example, for the cortex-m kernel, it supports only the Thumb-2 instruction set, so there is no special case, and the Thumb-2 instruction set can be used directly for the ARMV7 kernel.

In addition, the CORTEX-A8 core has an Neno unit that accelerates multimedia and signal processing algorithms. Neno technology includes single instruction multi-data smid instructions and vector floating-point VFPv3 instructions, so the compiler needs to support the SMID instruction set and the VFPV3 instruction set in order to achieve optimal performance of the kernel.

2.2. Compiling tools

Arm development from the source code to the final generation of the executable binaries need to rely on a system of development tools, such as C compiler, assembler, linker, debugger, binary conversion tools, etc., generally need a complete set of use. The following is a brief introduction to several commonly used arm integration development tools.

2.2.1. MDK

Keil because Keil C51 and is well known by the domestic engineers, and KEILMDK is Keil for ARM core development of integrated development environment. Keil was acquired by ARM, also adopted arm RealView compiler tool, make Keil MDK compile efficiency, compile quality, etc. all get corresponding promotion, is also arm official compiler. Keil MDK Support ARM7, ARM9, Cortex-m0, CORTEX-M3, cortex-m4 these low-end series of arm core. Its simple operation, highly optimized micro-Library, small package real-time operating system, and perfect GUI support enable it to rapidly develop various targeted applications and provide complete solutions for small embedded application development.

2.2.2. IAR

IAR supports many semiconductor companies ' microprocessors, supporting more than 20 different architectures of 8-bit, 16-bit, 32-bit cores. For example, IAR for 51 is used to develop a classic 51 microcontroller, IAR for AVR to develop Atmel AVR microcontroller, IAR for STM8 used to develop STMicroelectronics STM8 microcontroller and so on. The IAR for ARM is a tool set developed by IAR for ARM Core, its simple user interface, many powerful setting operations, such as automatic misra C rule checking, perfect C99 support and so on. The arm version of IAR supports each series of arm cores, including the Cortex-a8 kernel described in this chapter. IAR has good code optimization performance, high-quality code compilation, is a very good compiler tool.

2.2.3. DS-5

DS-5 is a comprehensive suite of end-to-end software development tools for ARM-supported Linux and Android platforms. ARM's own compilation tools have evolved in several versions, from the initial ADT to the ads, to the RVDS, to the current DS-5. ADT and ads have ceased to update for more than 10 years, far from meeting today's arm development requirements and should not continue to be used. The current DS-5 support arm's latest kernel, can be specific to the core pipeline instruction and other optimization, can be cortex-a7, cortex-a8, CORTEX-A9, CORTEX-A15 and other direct software simulation simulation. No one is more familiar with arm cores than arm, and there are reasons to believe that DS-5 will have higher code optimizations and higher code quality than other compiler tools.

2.2.4. GCC

GCC is a set of compiled tools developed by GNU and has been adopted as an official compilation tool by most UNIX operating systems, such as Linux. GCC also supports a multitude of processor architectures such as ARM, Alpha, MIPS, AVR, and so on. The GNU program has developed a large number of free open source projects, most of which are based on GCC development, although free of charge, without losing the corresponding commercial software. If you develop arm under the Linux operating system, choosing GCC will also have a large number of excellent open source projects, which is a thriving and attractive place for the Linux operating system. GCC is powerful and flexible, but the vast majority of its command-line based Makefile,shell scripts are uncomfortable for engineers who are accustomed to developing under Windows, but with an integrated development environment like Eclipse, GCC will also become easy to use.

Software development and compilation tools are irrelevant, can be based on their own use of the custom to choose a compilation tool. Due to the large number of users using IAR under Windows, the author will also develop s5pv210 based on IAR.

2.3. Other tools 2.3.1. Dnw.exe

For Samsung series CPUs, Samsung developed the Dnw.exe tool under Windows to aid in the development of its under-the-door chip. Dnw.exe supports two main functions of serial communication and USB communication, and supports downloading PC-side files to target board via serial port or USB, which will play an important role in the debugging and development stage.

Figure 2-1 Dnw.exe Tools

2.3.2. Sd/mmc Start the Burn tool

For the application processor, often support a variety of boot devices, s5pv210 also not for example, support SD/MMC boot, Onenand boot, NAND boot, ESSD boot, and so on. A variety of start-up methods, convenient according to the actual application needs, select the corresponding curing memory, reduce BOM cost. In particular, the SD/MMC start-up method, simply burn the code into the SD/MMC card on the PC, the target board can execute the code inside the SD/MMC card, without complicated operation and expensive burner. In the debugging development phase, the code can often be directly burned into the SD/MMC card run debugging, debugging through, and then through the SD/MMC card inside the bootloader code automatically SD/MMC card inside of the burning bootloader, kernel, file system and other binary code into the onboard NAND Flash and other cured memory, and then through the on-board curing memory to start.

SdBoot.exe for the author under Windows for the Samsung s3c2416 and s5pv210 two platforms developed SD/MMC start burning tools. SD/MMC boot requires the corresponding code format and needs to be burned into the SD/MMC card specified location, SdBoot.exe tool Set code format conversion and SD/MMC card burning in one, Can burn s3c2416 and s5pv210 two platform under the author of the bare metal bootloader,wince bootloader,uboot, tools easy to use.

Figure 2-2 SdBoot.exe Tools

3. s5pv210 Boot Mode

The s5pv210 supports a variety of boot modes, using the external pin om[5:0] to select the appropriate boot mode, PIN configuration corresponding to the boot mode see. The general design is not to use nor flash, because nor flash slow, can not be used to directly execute code, are to load into RAM execution, code storage can choose eMMC, Nand Flash and other on-board curing memory according to the actual situation.

Figure 3-1 om Boot pin description

wherein, SD/MMC Channel 0, Nand, ESSD, Onenand as the first boot device, if the first boot device fails, then try a second boot device (SD/MMC Channel 2), if the failure again, try the UART start, and then fail, it is USB boot, If it fails again, the START process is stopped.

To support the boot of external devices, the s5pv210 has built-in 64K ROM and 96K SRAM. wherein the 64K ROM code is located in 0x00000000, is the Samsung solidified into the chip code, called BL0. After a power-on reset, the BL0 code executes first, BL0 first shuts down the watchdog, initializes the instruction cache, stack, function, PLL, and system clock, copies the user code (BL1) to the internal SRAM 0xd0020000, verifies and verifies that the BL1 code is correct, and if it fails, The second boot device tries to start, and the test succeeds, then jumps to the user's BL1 code execution.

The user's BL1 code is up to 16K and can initialize the most basic system parameters at BL1, such as DRAM initialization, stack reset, coprocessor initialization, and then load the BL2 (or direct kernel) to the appropriate RAM location, and finally jump to BL2 (or kernel) execution.

The BL1 code has a specific format requirement because the BL0 code verifies that the BL1 code is correct to execute. The BL1 code must contain 4 words at the beginning of the header, the No. 0 Word and the 2nd Word will be BL0 to verify the correctness of the code, so the two words must truthfully reflect the BL1 code situation. The No. 0 Word is the size of the BL1 code (Byte), the maximum 16k, the 2nd word for the BL1 code of the test and, BL0 according to the size of the BL1 code to calculate the corresponding test and, and then the information head of the 2nd word comparison, if consistent, then jump to BL1 execution, otherwise think the test failed, try the second boot device.

Figure 3-2 Header Info

In addition, for Onenand/nand start-up equipment, BL0 in addition to testing the BL1 test and, will also test NAND ECC data, BL1 when burned into the NAND device, should also generate the corresponding 8/16-bit ECC data, written to the NAND spare region of the specified location, Otherwise, the ECC checksum failure will not start from the NAND device.

Figure 3-3 Nand ECC test

4. Appendix

SdBoot.exe Tools and User manuals

Http://pan.baidu.com/s/1i3CeAS9

S5PV210 Development Series One _ development environment and startup mode