Schematic diagram of the VHDL keyboard jitter elimination circuit and the complete code of the 4 × 4 keyboard

Dejitters circuit (1)

Eliminate jitter Circuit

In the figure, the button signal is first sent to the key foot, where CP is the clock pulse signal of the circuit (the sampling signal should be regarded as about 8 ms ). After the key signal goes through two levels of D Trigger delay, it is then processed using the RS trigger.

Here, the RS trigger frontend connection and non-gate processing principles are as follows:

1. Because the speed of pressing a button is up to 10 times per second, that is, the time of pressing a button is 100 ms, the press time can be estimated to be 50 ms. If the CP frequency of the sampling signal is 8 ms, the sampling can be 6 times.

2. If the unstable noise is less than 4 ms, sampling is performed once.

3. After the RS trigger is attached and-not, the SR configuration is only:

S	R	Dly_out
0	0	Unchanged
1	0	1
0	1	0

That is, when D0 is 1 and D0 is 1, The result s = 1, r = 0, dly_out will output 1. this indicates the key signal to be sampled and can be sampled twice consecutively. Therefore, it is determined that the key is pressed stably.

Similarly, if D0 is 0 and D0 is 0, the result s = 0, r = 1, and dly_out is 0. this indicates the key signal to be sampled, which can be sampled for two consecutive times. Therefore, it is determined that it is a stable release button.

Similarly, if D0 is 1 and D1 is 0, the result s = 0, r = 0; dly_out will remain unchanged.

D0 = 0, d1 = 1.

In short, one is output only after two sampling times, and zero is output only after two sampling times.

However, because the electronic clock jitter is eliminated for time counting, even if the output time of the dly_out signal in the eliminated figure is too long, the error of counting more than once occurs, therefore, a level-1 differential circuit is added.

Note: 1. The frequency of the pulse signal used by the jitter elimination circuit must be higher than that of the pulse signal used by other circuits; generally, the frequency of the Scan Circuit or LED display circuit is set to around 24Hz, and the frequency of the jitter elimination circuit is set to around Hz. The frequency of the two is usually 4 times or higher.

2. The signal stabilization time must be determined by the number of D triggers and CLK clock.

Dejitters circuit (2)

In fact, it is the same as the above principle. It is used to sample the rising edge of each pulse. After obtaining '1' several times in a row, it outputs '1'. After obtaining '0' several times in a row ', 0.

 

 

Download: VHDL 4*4 Keyboard Scan http://download.csdn.net/source/935493

Schematic diagram http://download.csdn.net/source/888299 of VHDL keyboard jitter elimination Circuit