SDRAM circuit Design Detailed



UDQM, LDQM: Data input and output shielding pin.
Used to control output buffering in read mode and to mask input data in write mode.
LDQM,UDQM these signal lines are for byte access and half-word access, LDQM control low eight-bit, UDQM control high eight-bit, so when to write in bytes, the high eight-bit screen off.

This paper introduces the addressing principle of SDRAM before the design of SDRAM circuit. SDRAM inside is a storage array, you can think of it as a table, and the principle of table retrieval, first specify the row, and then specify the column, you can accurately find the required storage unit, which is the basic principle of memory chip addressing, this table is called the logical Bank. Due to technical, cost and other reasons, it is impossible to do only a full-capacity bank, and due to the SDRAM operating principle, a single bank can cause very serious addressing conflicts, greatly reduce memory efficiency, so SDRAM internal division into multiple banks, the current SDRAM is basically 4 bank. The storage array is shown in Figure 1 :

Figure 1 　 SDRAM Storage Array

Figure 2 SDRAM PIN Configuration Scheme

Figure 2 is a configuration scheme for the SDRAMBank address provided by the s3c2440a Manual, and the SDRAM used to maintain the system is　hy57v561620ftp-h, its specification is 4*4m*16bit(using two pieces is to configure the bus width of the three bits), theBANK size is 4M*16=64mb, the bus width is The device size is 4*bank size =256mb, register configuration is (4M*16*4b) * *, according to Figure 2, The BANK address pin (ba[1:0]) on the SDRAM is connected to the s3c2440 a[25:24] .

figure 3 s3c2440a control address bus connection

Figure 3 is the Register control address bus connection, we use 2 SDRAM configured as the bus width of the three-bit, so the a[on the SDRAM 12:0] received the s3c2440 a[14:2] pin. The specific SDRAM Circuit Connection 4 shows:

Figure 4 　 SDRAM circuit Connection Diagram

SDRAM the address pin is multiplexed, when reading and writing SDRAM memory Unit, the operation process is to read and write address two times into the chip, each time by the same set of address lines into the address, two times into the chip on the addresses are called the line address and column address, They are latched into the inside of the chip by the line address latch and the column address latch. Here is a partial signal description of the chip:

Nsras :SDRAM line Address Select communication number

Nscas :SDRAM column Address Select communication number

NSCS :SDRAM chip selection signal (optional Bank6 as SDRAM space, can also choose Bank7)

nwbe[3:0] :SDRAM data masking signal

Sclk0[1] :SDRAM clock signal

SCKE :SDRAM clock allows signal

Ldata[0:31]:32 bit data signal

LADDR[2:14]: Row and column address lines

Laddr[25:24] :Bank selection Line

SDRAM (Synchronous dynamic random Access memory, synchronous RAM) is usually called memory. In our current use of the PC, refers to the memory, in fact, is SDRAM, but it is his upgrade version, such as DDR memory, DDR2 memory, DDR3 memory, and so on, most of the video card is SDRAM.

Memory is the code of execution space, take the PC as an example, the program is stored in the form of a file in the hard disk, the program is loaded into memory by the operating system before running, because the memory is RAM (random access memory ), The address can be used to locate a byte of data, the CPU executes the program when the value of the PC is set to the start address of The program, the CPU will be in sequence from the memory, decoding, execution, before the memory is not initialized, memory is like a house is not built, is unable to read and store data , so we have to initialize the memory in order for the program to run in memory.

before describing how the memory works, it is important to understand how the storage device is stored : Rom,ram

ROM (read-only memory): read-only memory, a solid-state semiconductor memory that can read only pre-existing data. The feature is that once the data is stored, it can no longer be changed or deleted. It is usually used in electronic or computer systems that do not require frequent changes to the data and will not disappear due to power off. such as: The BIOS inside the PC.

RAM (random access memory) : Random access memory, the contents of the storage unit can be arbitrarily removed or deposited on demand, and the speed of access to the location of the storage unit independent of the memory. It can be understood that when you give a random, valid access address, RAM returns its stored content (random addressing), and its access speed is independent of the address. This kind of memory loses its storage content during power loss, so it is mainly used to store the program which is used randomly in short time. The memory address in a computer system is a four-byte aligned address (32-bit machine), CPU fetch, execution, storage is through the address, so it can be used to do memory.

RAM according to hardware design, random memory is also divided into dram (dynamic RAM) and SRAM (static RAM) random memory.

DRAM: Its basic original is a small capacitor, the capacitor can be on two plates for a short period of time to retain the charge, can be through the polarity between the voltage difference between 0 and 1 of the computer, due to the physical characteristics of the capacitance, to regularly charge for it, Otherwise the data is lost. The charging process of the capacitor is called refresh, but the production process is simple, small size, easy to integrate, often as a computer memory to make the original. For example: The memory of the PC, SDRAM, DDR, DDR2, DDR3, etc., disadvantage: Due to periodically refresh the storage media, access speed is slow.

SRAM: It is a memory with a static access function, it can save the data stored in it without needing to refresh the circuit. Therefore, its access speed is fast, but large size, power consumption, high cost, commonly used for storage capacity is not high, but fast access, such as the CPU L1 Cache,l2cache (first level, level two cache), register.

to meet the needs of development, jz2440 three storage media at the Factory:

(1) NOR FLASH (2M): ROM memory, usually used to save bootloader, boot system boot

(2) NAND FLASH (256M, different model, Nandflash size): Save operating system image file and file system

(3) SDRAM (64M): Memory, execution program

NOR FLASH: It is characterized by support for XIP in-chip execution (execute in place) so that the application can run directly in Flash flash memory without having to read the code into the system RAM, which means it can be randomly addressed. NOR Flash costs higher.

NAND FLASH: It provides very high cell density, high storage density, and fast write and erase speeds. The cost is low and XIP is not supported. Can be used in embedded data storage media. such as: Mobile phone memory card, SD card and so on.

s3c2440 address space:

s3c2440 External led to 27 address line addr0~addr26, which can be addressed up to 128MB, and s3c2440 address space can reach 1GB, this is because s3c2440 will be 1GB of addressing space into 8 banks (BANK0~BANK7), Each bank corresponds to a chip selection signal line NGCS0~NGCS7, when accessing bankx, NGCSX pin level pull low, used to select the foreign connection device, s3c2440 through 8 signal lines and 27 address lines, you can access 1GB. As shown in the following:

SDRAM storage structure:

First, let's introduce a set of signals provided by the CPU for SDRAM:

1 . SDRAM clock effective signal Scke;

2 . SDRAM clock signal sclk0,sclk1;

3 . data Mask signal dqm0,dqm1,dqm2,dqm3;

4 . SDRAM chip selection signal nSCS0 (IT and nGCS6 are the same pin two functions);

5 . SDRAM line address strobe pulse signal nsras;

6 . SDRAM column Address strobe pulse signal nscas;

7 . write the allowable signal nwe (it is not dedicated to SDRAM).

The internal SDRAM is a storage array, the array is similar to the table, there are rows, columns, so we want to access (read, write) a unit, we must first specify a row address, a column address, so that the unit is found, this is the basic principle of SDRAM addressing. The units here are generally referred to as storage units, and the entire table is called The logical Bank (Logical Bank, L-bank), and generally each SDRAM will have 4 L-bank. The logical structure of SDRAM is as follows:

JZ2440 is the selection of 2 pieces of hy57v561620ftp-h composed of 64MB, 32-bit memory, 32MB capacity per piece, 16-bit data bus. Schematic diagram is as follows:

As can be seen in the figure, the line address, column address shared address line Addr2~addr14 (BANK6 bit width of 32,addr0, 1 is not used), using Nsras, nscas two signals to distinguish them. In the jz2440 Development Board, use two address lines ADDR24, ADDR25 as the L-bank selection signal, SDRAM chip k4s561632 row address number is 13, column address number is 9, so when the Nsras signal is valid, addr2~ ADDR14 is a line address signal, which corresponds to the 32-bit address space of the bit[23:11]; when the nscas signal is valid, ADDR2~ADDR10 sends a column address signal, which corresponds to the bit[10:2 of the 32-bit address space].

Focus on the SDRAM chip k4s561632 address line A0~A12 Description:

The chip each bank has 13 rows (RA0~RA12), 9 columns (CA0~CA8), row addressing using A0~A12, column addressing time-sharing, using only ca0~ca8. The NRAS, NCAs pin, which identifies the current row or column addressing, which enables time-sharing of the address line.

jz2440 Development Board is composed of two 16-bit SDRAM chip in parallel 32 bits of the bit width, and the CPU 32 data cable data0~data1 connected. SDRAM is connected on the BANK6, the starting address is 0x30000000, so the access address of SDRAM is 0X30000000~0X33FFFFFF, the size is 64MB.

Look at the above content, there are some things that make me baffled, may be too stupid, but finally I want to understand.

1, why two SDRAM chips in parallel, the capacity size is 64MB?

The reason is this: the SDRAM chip has 4 banks, each bank's row address number is 13, the column address number is 9, by two block 16 bits of SDRAM chip in parallel to make up 32 bits of the bit width, and the CPU 32 data line data0~data1 connected. Then its storage space is (2^13*2^9*4*32bit)/8 = 2^26*8BIT/8 = 2^26 Byte = 64MB

2. Why is the A0 address pin of the SDRAM chip connected to the A2 pin of the arm chip?

According to the previous question, it is known that the SDRAM storage space is 64mb,s3c2440 to address 64MB, which requires 26 root of the addressing line. The data bus bit width of SDRAM is 32 bits, i.e. 4 bytes of data is transmitted at one time by the schematic diagram. Therefore, we can understand that an address space actually corresponds to 4 bytes of data , in fact, the real addressing space is only 16MB, only 24 address lines (line address line 13, column address line 9 root, and L-bank Select the signal of A24, A25 two address line, A total of 24) is sufficient, so that the s3c2440 side does not need to connect all 26 address lines to the SDRAM chip, only need to give a high 24-bit address (a2~a25), equivalent to 4 bytes per transmission on the data bus, the address space of the third (A2) increased by 1, That is, A0 and A1 can not be answered. The A0 and A1 at this time should be low level. The SDRAM chip then finds the corresponding address space based on the row address, column address, and L-bank selection signal given by s3c2440, and sends 4 bytes of that address space to the data bus. And so on, the data bit width is 8 bits, on ARM chip's A0 connect SDRAM a0,16 bit to A1 a0,32 bit on A2 to connect A0.

Another detail is why the BA0~BA1 of the SDRAM chip is connected to the LADDR24~LADDR25 pin of the s3c2440 chip?

because, hy57v561620 is a 32MB SDRAM chip, we know that 32MB of storage space requires 25 address line addressing, because the BA0~BA1 pin determines the access to the first bank, that determines the maximum storage space of two bits , so you need to connect BA0~BA1 with the highest two bits in the 25 address lines of s3c2440, so that you can meet the mapping requirements for addressing.

SDRAM circuit Design detailed