Select the AMD K8 CPU. Do you pay attention to the memory combination?

For more information about the system bus before AMD K8, see PC architecture series: Development History of CPU, RAM, and IO bus.
 
One of the biggest changes to AMD's K8 processor is that the CPU core integrates the Memory Controller (Memory-Controller ). This means
The CPU can directly access the memory (RAM), instead of connecting to the beiqiao chip through the system bus as before, or the beiqiao chip can no longer need
The memory controller function is required. Then, with the passing of the "classic" system bus structure, the concept of FSB no longer exists, and the clock frequency for other work parts
There is also a new method, which is the "Frequency Division" or "Frequency Division" (the Clock Divider) mechanism in AMD K8!

Before giving a detailed description of the K8 division mechanism, let's review the system structure before K8. For K7, the system structure is generally the same as the Intel series structure.
There is no difference. It is all FSB mode:

Looking at the system structure of K8, we can see that the biggest difference is that the CPU is directly connected to RAM, and there is a new face,
Is the HyperTransport bus specification, replacing the traditional FSB technology!

Many motherboard manufacturers have introduced Single-core Boards. The traditional concept of the north-south bridge structure is vague.
Integrates all functions except the memory controller function, and even the video card function!

The problem arises. Since the concept of FSB is gone, who will provide the external frequency of the CPU, which originally uses the FSB operating frequency (not the equivalent frequency) as a reference?

Please refer:

First, let's explain what is a PLL (Phase Locked Loop). Simply put, it is to multiply the original input signal of the crystal oscillator to the input of a certain working frequency.
The BASE-CLOCK generated after the PLL is 200 MHz.

Next, the problem arises: In the original K8 architecture, both the memory frequency and the hypertransport clock frequency are based on the CPU frequency!

We finally see the long-awaited memory divider. How can we use the memory with the CPU? We have the following formula:
CPU frequency/memory divider = DDR/DDR2 memory bus frequency = DDR/DDR2 memory operating frequency * 2

* Note: If memory divider is not an integer, for example, 4.6, you must set memory divider to 5 to avoid Memory overclock operations.

For amd AM2 athlon 64 3200 +, the CPU frequency is 200 MHz * 10 = 2000 MHz.

If we use DDR2 667 memory

--> The data transmission rate is 667 MHz, the memory bus frequency is 333 MHz, and the memory operating frequency is 166 MHz.
--> Therefore, memory divider must be set to 6, that is, 2000 MHz/6 = 333 MHz = 166 MHz * 2.

If DDR2 800 memory is used

--> The data transmission rate is 800 MHz, the memory bus frequency is 400 MHz, and the memory operating frequency is 200 MHz.
--> Memory divider is 5, that is, 2000 MHz/5 = 400 MHz = 200 MHz * 2

However, for AMD AM2 athlon 64 3500 +, the CPU frequency is 200 MHz * 11 = 2200 MHz.

If we use DDR2 667 memory,

--> Memory divider: 2200 MHz/333 = 6.6, which must be set to 7.

In fact, DDR2 667 memory bus frequency is 2200 MHz/7, and its actual transmission rate is: (2200 MHz/7) x 2 = 629 MHz <667 MHz,
In fact, the memory has not fully utilized the maximum function, but there is no way!

To sum up, it is best to select an amd cpu or select DDR2 Memory Based on the CPU clock speed, preferably:

1. The smaller the memory divider, the better.
2. The closer the actual memory operating frequency is to its rated value, the better!