[Serialization] An example of FPGA-based 6-segment display decoder-8-3 BCD

[Serialization] FPGA OpenGL series instances 

8-3 BCD seven-segment display decoder in the format

I. Principles

The 7-segment digital tube uses a combination of different light-emitting segments to display different digital data. To try the digital tube to display the numbers represented by the digital, you must translate the digital data into a decoder, then the block used by the drive is illuminated. The structure is shown in Figure 1.1. For example, to display the value 5, the segments A, F, G, C, and D must be illuminated.

 

Table 1.2 3-8 decoder truth table

II. Implementation

In the design file, enterCode

 1   'Timescale  1 NS  /     1  PS
  2   
  3   Module bcd7seg (Y, );
  4   
  5   Input [  3  :  0  ];
  6  Wire [  3  :  0  ];
  7   
  8   Output [  6  :  0  ] Y;
  9   Wire [  6  :  0 ] Y;
  10   Assign y  = ~  Y_R;
  11   Reg [  6  :  0  ] Y_R;
  12   
  13   Always @ ()
  14   Begin
 15   Y_R  =     7  '  B1111111;  
  16       Case  ()
  17     4  ' B0000: Y_R = 7  '  B0111111;  //  0  
  18       4  '  B0001: Y_R = 7  '  B0000110;  //  1  
 19       4  '  B0010: Y_R = 7  '  B1011011;  //  2  
  20       4  '  B0011: Y_R = 7 '  B1001111;  //  3  
  21       4  '  B0100: Y_R = 7  '  B1100110;  //  4  
  22      4  '  B0101: Y_R = 7  '  B1101101;  //  5  
  23       4  '  B0110: Y_R = 7  '  B1111101; //  6  
  24       4  '  B0111: Y_R = 7  '  Bda-111;  //  7  
  25      4  '  B1000: Y_R = 7  '  B1111111;  //  8  
  26       4  '  B1001: Y_R = 7  '  B1101111;  // 9  
  27       4  '  B1010: Y_R = 7  '  B1110111;  //  A  
  28       4  ' B1011: Y_R = 7  '  B1111100;  //  B  
  29       4  '  B1100: Y_R = 7  '  B0111001;  //  C  
 30       4  '  B1101: Y_R = 7  '  B1011110;  //  D  
  31       4  '  B1110: Y_R = 7 '  B1111001;  //  E  
  32       4  '  B1111: Y_R = 7  '  B1110001;  //  F  
  33      Default  : Y_R  =     7  '  B0000000;  
  34     Endcase
  35   End
  36   
  37  Endmodule