[Serialization] [FPGA black gold Development Board] those issues in the FPGA-serial port module (11)

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• 3.4 experiment 10: Serial Port Module
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3.4 experiment 10: Serial Port Module

Single Chip Microcomputer? Serial Port? These are already well-known combinations. But do you understand the small part of serial transmission? Let's leave the hardware interface aside (basically nothing to talk about) and experiment in the traditional serial port. On the surface of the serial port, we only configure and query the registers of the single chip microcomputer to implement serial port operations ~

Actually, do you know what happened during the transmission of the serial port? You can build a model for the serial port by Using OpenGL at the underlying layer.

Each frame of data transmitted through the serial port (11 bits)

bit	bitwise effect / TD>
0	Start position
1 ~ 7	data bit
9	check bit
10	Stop bit

The "High Level" is the default status on the serial port bus. When a frame of data starts to be transmitted, it must be lowered first, which is the role of 0th bits. After 0th bits, there are eight data bits. These eight data bits are the most meaningful items in a frame of data. The last check bit or stop bit is basically meaningless and serves the same purpose as naming.

Another important parameter for serial transmission is the "baud rate ". Many of my friends have misunderstood that the "baud rate" is the transmission speed of serial transmission, which is basically correct. However, in the microscopic sense, the "baud rate" is the "cycle of a single bit", that is, "the time of a single bit ".

Common baud rates include 9600 bps and 115200 BPS (bit per second ). "9600 bps" indicates that 9600 bits can be transferred per second. However, the formula for calculating the "one-digit period" is exposed.

One-digit cycle = 1/BPS

= 1/9600

= 0.000104166666666667

From the above formula, we understand the fact that 9600 bps, one data occupies 0.000104166666666667 S. For a frame of 11-bit data

0.000104166666666667x11 = 0.00114583333333334

The data can be transmitted within one second.

1/0.00114583333333334 = 872.727272727268

872.727272727268 frames of data.

Of course, this is only calculated in numbers, but there are actually many invisible latency factors.

Experiment 10: Serial Port receiving module

In terms of serial port reception, it is basically a "sampling" operation. When you understand the meaning of "BPS", it is very easy to receive serial ports.

In experiment 10, you need to create rx_module.v. Rx_module.v is a combination module, mainly including detect_module.v, bps_module.v and rx_control_module.v, two function modules, and one combination module.

The input of detect_module.v is connected to the unreasonable pin Rx. It mainly detects the 0th bits of a frame of data, that is, the start bit, and then generates a high pulse to rx_control_module.v through h2l_sig, to indicate that a frame of data has been received.

Rx_bps_module.v is a function module that generates a regular baud rate. In other words, it is a module for configuring the baud rate.

When rx_control_module.v increases count_sig, bps_module.v generates a scheduled value for rx_control_module.v through bps_clk.

Rx_control_module.v is the core control module. The configuration of the serial port is mainly one frame of 11-bit data, focusing on eight-digit data bit, ignoring the start bit, check bit and check bit. When rx_en_sig increases, this module starts to work. It will collect data from rx_pin_in. When a frame of data is received, a high pulse will be generated to rx_done_sig.

How is "Collection" realized?

First, you can guess when the data is the most stable? As shown in, data is collected in the middle of each data. Input a frame of data in rx_pin_in. When detect_module.v detects a low level (start bit), rx_control_module.v and rx_bps_module.v generate a scheduled time (consistent with the baud rate of rx_pin_in ), however, rx_bps_module.v is generated in the middle of each bit of time.

The 0th-bit data is ignored, and the next 8-Bit Data bit is collected. The last check bit and stop bit are ignored. One thing you must pay attention to is that the serial data transmission starts from the lowest Bit to the highest bit ".

The above content is mainly about rx_module.v. For full-duplex serial ports, rx_module.v must be independent from tx_module.v, so rx_en_sig and rx_done_sig are required.

Source code: detect_module.v

Well! The function module detect_module.v is also very familiar, and the function module is designed to check the level from high to low. When the level is detected to be high or low, a high pulse is output in 31st rows.

Rx_bps_module.v

The transmission speed of 9600 bps makes the cycle of one bit of data 0.000104166666666667 S. To obtain the above timing at a 20 MHz clock frequency:

N = 0.000104166666666667/(1/20 MHz)

= 2083

If it is counted from 0 to 2083-1, that is, 2082 counts (20 rows ). However, if data collection requires "in the middle of the cycle", the result is 2082/2, and the result is equal to 1041 (29 rows ). Basically, rx_bps_module.v starts counting only when count_sig is high (22 rows.

Rx_control_module.v

In ~ Row 61 is the core control function of rx_control_module.v. In line 37, it indicates that this module will not work if rx_en_sig does not pull high. (The iscount flag register is defined in line 26. In order to make the rx_bps_module.v output BPS timed) when the rx_control_module.v module is enabled, the module will be in the ready state, once detect_module.v detects a level change (41 rows), step I enters the 0th-bit collection. However, the iscount flag register is also set to logic 1, rx_bps_module.v starts to generate the baud rate.

We know that rx_bps_module.v is generated in the middle of each data ". In 43 ~ In row 44, the first time the data is collected at the scheduled time is 0th bits (start bits. In 46 ~ Row 47, which periodically collects eight-digit data bits. each bit of data is stored in the RDATA register from low to highest.

49 ~ The 53 rows are the last two rows of regular collection (check bit, stay bit), while taking a negligible attitude. When you enter ~ 59 rows. This indicates that the collection of one frame of data has been completed. At last, a high pulse of the completion signal is generated. At the same time, iscount is set to logic 0, that is, rx_bps_module.v is stopped.

65 ~ Row 67: The iscount flag register is the count_sig output drive, the RDATA register is the rx_data output drive, and the isdone flag register is the rx_done_sig output register.

Rx_module.v

Tutorial 10:

When rx_module.v is combined with a module, after everything is organized, only set aside. Input rx_pin_in and rx_en_sig to output rx_data and rx_done_sig. As long as you know the basic operations of rx_module.v, this module can be easily controlled.

The most difficult part of experiment 10 is the "timed Collection" part. The reason why I mentioned above is that most of the students have misunderstandings about the "baud rate", that is, the relationship between them. If you think from another perspective, the shorter the time a single bit occupies, the more places that can be transferred within 1 second, and the higher the transmission rate.

In the test, rx_bps_module.v configures the baud rate. However, rx_control_module.v configures the "Data bit width", "parity check", and "Stop bit width. However, in general applications, "one-bit start bit, eight-Bit Data bit, one-bit check bit, and one-bit stop bit" has become popular. Of course, the baud rate is 9600 bps or 115200 BPS, depending on the distance.

The lower the baud rate, the slower the transmission speed, the longer the distance. The higher the baud rate, the shorter the distance supported, although the data transmission volume is high in a short period of time. We can regard distance and baud rate as positive and negative ratios.

Extension diagram after completion:

Conclusion:

The "timed Collection" part is hard to understand, but after careful consideration, you will find that this writing method is logical.

Demonstration of experiment 10:

In this chapter, for example, rx_module_demo, a control module is created to call rx_module.v.

At the beginning, control_module.v will increase rx_en_sig to enable rx_module.v. When a burst of data is passed in through rx_pin_in, rx_module.v receives the data and outputs the output to rx_data, and generates a high pulse to rx_done_sig. When control_module.v receives the high pulse of rx_done_sig, It outputs the "first four bits" of rx_data to four bits of LED resources.

Demonstration source code of experiment 10: control_module.v

In 22 ~ Line 27 is all about this control module. At the beginning (27 rows), Isen is set to logic 1. This flag registers drive rx_en_sig in 32 rows. In other words, when rx_module.v is ready, the same control_module.v waits for the notification of rx_done_sig (25 rows ). Once a frame of data is received, rx_done_sig generates a high pulse, and RDATA is assigned the value of rx_data. At the same time, Isen is set to logic 0 (26 rows ). In the next instant, control_module.v sets Isen as logic 1 again to prepare for receiving the next set of data.

Rx_module_demo.v

This is a combination of modules demonstrated in one of the 10 experiments, nothing special. The connection relationship is basically the same as that of the "image.

In the 45 rows, perform "Load Reduction" on the output to the first four digits.

Demonstration of experiment 10:

This demo is mainly used to send the "Serial Port debugging assistant" in hexadecimal format. For example, if 0f is output, the four LEDs will be highlighted and 0a will be output, the fourth and second LEDs are on.

Extension diagram after completion:

Demonstration conclusion of experiment 10:

When designing a combination module, the requirements are very high. In addition, this demo demonstrates how rx_module.v is called.

Experiment 10 II: Serial Port sending module

After one of the experiments, I have basically mastered the concept of "baud rate? In this chapter, the experiment "baud rate" is still a very important role to maintain.

Is the tx_module.v combination module. Compared with rx_module.v, tx_module.v is less than detect_module.v because it is not required when a frame of data is sent through the serial port.

Tx_bps_module.v is also used as a "scheduled" function. When tx_en_sig is low, it is in sleep state. Once tx_en_sig increases, tx_bps_module.v starts counting. Then, a high pulse is periodically generated and sent to tx_control_module.v through bps_clk.

Tx_control_module.v control module is the most central part. When tx_en_sig increases, tx_bps_module.v starts counting at the same time. Tx_control_module.v sends the tx_data value to tx_pin_out in a rhythm based on the time generated by tx_bps_module.v. After a frame of data is sent, a high pulse of tx_done_sig is generated.

Tx_module.v is different from rx_module.v in that rx_module.v is "Scheduled Collection", while tx_module.v is "scheduled sending ". Assuming that the baud rate I configured is 9600 bps, this module will generate a high pulse to tx_control_module.v every 0.000104166666666667, the control module sends one-bit data at this time.

If the number of frames per frame is 11 characters, tx_bps_module.v needs to be generated for 12 times.

Source code: tx_bps_module.v

Tx_bps_module.v is the baud rate (20 rows) configured as 9600 bps. It is basically different from rx_bps_module.v. However, it is worth noting that its current job is "timed sending ". However, one thing that may confuse readers...

We know that bps_clk is generated in the middle of "one-bit data". If this mode is easy to understand in the role of "timed Collection, but what is the difference between the "timed sending" mode?

There are three "timed sending" in the left figure. Each "timed sending" occurs when the count is 12 'd1041. The number of attempts made by the reader indicates the difference between the two "timed sending" messages. How many counts are there? That's right. It's 12 'd2082 counts. Now I understand what's going on! The difference between the generation of the previous timing and the generation of the next timing is the focus, that is, the "one-bit data cycle" is defined between two timing periods.

Tx_control_module.v

Compared with rx_control_module.v, tx_control_module.v is relatively simple. When tx_en_sig is increased (32 rows), the control module starts to work (tx_bps_module.v starts counting at the same time ). Every time tx_bps_module.v generates a scheduled high-pulse bps_clk, tx_control_module.v will send one bit of data.

The 0th-bit data is the start bit. Therefore, the RTX register is assigned a value of 0 (36 rows ). The next eight bits are data bits. tx_control_module.v assigns the data to the RTX register (39 rows) from tx_data to the highest bits ). However, the last two digits are both the check bit and the stop bit. If there is no special requirement, simply enter logic 1 (41 ~ 45 rows ). Finally, a tx_done_sig high pulse (47 ~ 51 rows ).

The output of row 58 tx_done_sig is driven by the isdone flag register. However, the output of tx_pin_out is driven by the RTX register.

Tx_module.v

The line in tx_module.v of the combination module is basically the same as that in the "image. However, in the case of 24 rows, the count_sig input is directly connected by tx_en_sig.

Tutorial 10 II description:

The transmission module tx_module.v is basically compared with rx_module.v for modeling and simplicity, as long as you have a good grasp of the differences between "timed Collection" and "timed sending.

Tx_bps_module.v still plays the role of configuring the "baud rate. The function of tx_control_module.v is to package one-byte data and send it in a frame format. If you want to add "check bit", set different "Data bit width", or set different "stay bit width", depending on the purpose. A common application has one start bit, eight data bits, one check bit, and one stop bit. If there are no special requirements, you can fill in the check bit.

Extension diagram after completion:

Conclusion:

Tx_module.v can be regarded as an independent module. In order to call it better, the tx_en_sig and tx_done_sig are useful for future calls.

Demonstration of experiment 10 II:

It is a combination module demonstrated by experiment 10 2. Control_module.v in tx_module_demo.v sends 0x31 data to tx_module.v every second.

At first, control_module.v outputs data to tx_data, and then increases tx_done_sig to start tx_module.v. When tx_module.v is sent to a frame of data, a high pulse is generated for tx_done_sig to indicate that the transmission is complete.

Demonstration source code for experiment 10 II: control_module.v

The first row is a definition constant of 1 second, ranging from 23 ~ 29 is a 1-second timer. Control_module.v sends 0x31 data per second. In other words, it sets the Isen flag register once per second. When Isen is set, tx_module.v starts to work. After a frame is sent, tx_done_sig generates a high pulse. This causes (42 rows) control_module.v to assign a value to the RDATA register and reset the Isen flag register. Until the next second arrives, the Isen mark register will be set again.

Tx_module_demo.v

This combination module is relatively simple and nothing special.

Demonstration of experiment 10 II:

In the demonstration of experiment 10 second, "Serial Port debugging assistant" will always show 1... if it is displayed in hexadecimal format, the result is 31, and the interval between each sending is 1 second.

Completed extension diagram:

Demonstration conclusion of experiment 10 II:

This demo demonstrates how to call tx_module.v.

Tutorial 10:

As I mentioned earlier, the serial port is executed in full duplex mode. When modeling, we should consider that "sending" and "receiving" are independent modules, or "sending" and "receiving" are parallel operations.

Whether it is the sending module or the receiving module, xx_bps_module.v controls the configuration of the baud rate. However, xx_control_module.v controls the configuration of one frame of data.

In addition, to call this module well, done_sig plays an important role. Do you still remember the traditional serial port experiment? On single-chip microcomputer, we use the "interrupt" or "query" method to know the working status of each module. However, the modeling in experiment 10 involves the middle of the two methods, or it should be called "Trigger.

I have said in the past Lab 8. At the micro level, each module is executed independently. However, some modules are quite special. Normally, they are in the ready state on the rising edge of the clock. Once there is a "Trigger" signal, it will work immediately. In this chapter, the experiment done_sig can be regarded as a "Trigger Signal" for "complete feedback ".

Conclusion:

The "low-level modeling" in experiment 10 is relatively simple. A serial port module is divided into two modules: the "sending module" and the "receiving module ". However, each module is divided into "Small Module", and each "Small Module" has its own functions.

For example, xx_bps_module.v is used to generate timing, and xx_control_module.v is used to configure the format of one frame of information data. At last, leave "xx_en_sig" and "xx_done_sig" on the Combination module for convenient calling.

In fact, experiment 10 involves a lot of basic knowledge about "sequential imitation operations" (previous experiments also involve one point ), because the "modeling structure" of "sequential operations" has the iconic start_sig and done_sig.

For more information, see the next chapter.

Summary:

Well! When you see this, you have mastered the most basic "low-level modeling" modeling ideas. The most important part of this chapter is "graphics" and "principles ". Because of the shortcomings of "low-level modeling", both "graphics" and "standards" can be effectively overcome, and "unexpected results" are also produced ". What is this "unexpected effect? I don't want to talk about anything, because that feeling is really not something that can be expressed in words... I guess readers gradually feel the "Incredible" feeling?