[Serialization plan] [everyone learns FPGA/FPGA Together]

Source: Internet
Author: User
ArticleDirectory
    • Part 1 Introduction to software
    • Part 2 Introduction to OpenGL
    • Part 3 exercise with OpenGL
    • Part 4: Part 3
    • Part 5 Time Series Constraints
    • Part 6 software skills
Description

There is no link to the unfinished document.

Comments

A lot of feedback shows that many FPGA beginners are passionate at the beginning, but if they are not getting started for a long time, some people will gradually lose their interest and confidence in FPGA learning. Why? The reason is as follows:

    1. At present, there are a large number of FPGA development boards on the market, but in most cases, the manufacturers provide FPGA beginners with only some simple routines.CodeThere is a serious lack of manual documents for FPGA beginners.
    2. Many FPGA design books on the market are copied from each other and translated into foreign languages. Although the content is wide-covering, some books cannot be copied, and some details may be omitted, misleading beginners.
    3. Most FPGA beginners do not have the habit of reading manual frequently. Generally, the technical details we do not know are described in the relevant manuals. Although most of the manuals are in English, reading them often not only improves our ability to discover technical problems and solve technical problems, but also improves our ability to read in English.
    4. Impetuous, some FPGA beginners, blindly collect too many project instances, a little bit of water, seriously lack of research on basic knowledge.

For the current situation (10000 nonsense sentences are omitted for the moment )......

Directory Part 1 software introduction
    1. Quartus II 10.0 Installation Guide
    2. Verilog us II Getting Started Guide designed with OpenGL
    3. ModelSim Getting Started Guide designed with OpenGL
Part 2 Introduction to OpenGL 1 Integrated Circuits
    1. Logic Gate Circuit
    2. Multi-path selector and multi-path decomposition Tool
    3. Encoder and decoder
    4. Arithmetic Operation Circuit
2. Time Series Circuit
    1. Triggers and latches
    2. Register
    3. Shift Register
    4. Binary counter
    5. FIFO Cache
    6. Divider
    7. Finite State Machine FSM
    8. Finite State Machine fsmd with data path

3 important topics

    1. Blocking assignment and non-blocking assignment
    2. Parameters and constants
    3. Use a signed number
    4. Use functions in combination
    5. Structure of the test platform
Part 3 exercise part 1 peripheral Experiment
    1. Marquee
    2. Flow Lamp
    3. Seven-segment digital tube
    4. Shake button
    5. 4x4 matrix keyboard
    6. Lcd1602
    7. PS2 mouse
    8. PS2 keyboard
    9. VGA Image
    10. VGA text
    11. PWM stepper motor
    12. Tlc549 serial ADC
    13. Tlc5620 serial DAC
    14. 74hc595

...

2 storage experiment
    1. On-Chip Rom
    2. On-chip RAM
    3. On-Chip FIFO
    4. SRAM

...

3 interface experiment
    1. UART Transceiver
    2. SPI Master/Slave controller

...

4 Algorithm Getting started lab
    1. Adder
    2. Multiplier
    3. Divider
    4. Calculate the positive cosine of CORDIC

...

Part 4: Part II performance issues
    • Performance Benchmark
    • Some experiences in writing the latency functions of the niosii
Timer Problems
    • Sys_clk_timer
    • Timestamp_timer
    • Watchdog_timer
OS Problems
    • How to run μC/OS-II
DMA Problems
    • [Transfer] DMA Transmission Based on niosii
Interruption Problems
    • Differences between sys/alt_irq.h of niosii 9.1 and earlier versions
    • Pio interrupt and timer interrupt
    • [Switch] Question about the interruption of niosii 9.1 SP1
Curing Program Problems
    • Programs cannot be solidified using 9.0sp2, 9.1, and 9.1sp2
    • Notes for using the sni ii sbte Flash program
Custom peripherals
    • Required information for custom peripherals
    • Simple Design of The aveon-mm interface of lcd12864 (st7920)
    • Register ing methods: library and register operations
    • Simple Design of the SRAM aveon-mm Interface
    • Dynamic and Static addressing
Case study: Simple Digital Photo Frames
    • Quartus II (hardware)
    • Niosii sbte part (software part)-configuration work
    • Ios ii sbte part (software part)-SD card (SPI mode) Driver
    • Niosii sbte part (software part)-TFT-LCD (Controller for ili9325) Drive
    • Niosii sbte part (software part)-read image files from the SD card and display them on the TFT-LCD
    • Niosii sbte part (software part)-Optimization
    • Sony II sbte part (software part)-ads7843 touch screen driver test
Part 5 Time Series Constraints

...

Part 6 software skills Part 1 software skills
    • Two common methods for Pin allocation in Quartus II
    • How to Use the JTAG mode in Quartus II to solidify the program into the PV
    • A work und to the problem of being unable to edit and view Chinese characters using the qii 10.0 Compiler
    • How to convert a HDL file to a BSF file in Quartus II
    • How to Use Debussy + Modelsim to quickly view the pre-simulation waveform
    • How to eliminate pointer targets in passing argument n of 'func _ XXX' differ in signedness warning
    • [Switch].In Windows 7, retrieve the lost "Run as niosii hardware" in the niosii eds 9.1"
2. intractable diseases
    • How to install the USB-blster driver on Windows 7 32
    • How to properly unplug the JTAG simulator of the FPGA Development Board, such as USB-blster
    • How to Set Data [1]/asdo and flash_nce/ncso to use as regular I/O in Quartus II 10.0 when using cyclone III

3 FAQ

    • Where is the driver of Altera USB-blster?

    ...

    Recommendation blog


      • However, FPGA engineers in practice

      • Really Oo no double book
      • Privileged's blog-always loyal to your dreams when you are young!
      • Crazybingo
      • Black gold FPGA Development Board

    ...

    Reference

    0. terasic. de2_115_v.1.0_cdrom> de2_115_tutorials

    1. Stephen Brown, Zvonko vranesic. Fundamentals of digital logic with OpenGL design 2nd edition. Mc Graw Hill

    2. Huang zhicun. Summary for IEEE 1363-2001

    3. Design Example of Altera. OpenGL

    4. Altera. Recommended HDL coding styles

    5. Zhuo xingwang. Digital System Application Design Based on OpenGL 2nd

    6. Zhou ligong. EDA experiment and practice. Beijing University of Aeronautics and Astronautics Press

    7. Liu fuqi, Liu Bo. detailed introduction to the example of designing the applications of the OpenGL. E-Industry Press

    8. Pong P. Chu. FPGA prototyping by MAID: Xilinx Spartan-3 version. Wiley

    9. fpga4fun

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