Setup time and hold time

The settling time and retention time are throughout the timing analysis process. As long as the synchronous timing circuit is involved, there is bound to be a rising edge, falling along the sampling, then can not avoid the two concepts of setup-time and hold-time.

Series Catalogue

Timing Closure: Basic concepts

Setup time and hold time

OFFSET in

OFFSET out

1. What is Setup-time and Hold-time

Between input, output, or register-register, the setup time and hold time are mentioned whenever a sample is designed to the rising/falling edge of the clock. These two indicators indicate that the device itself is not ideal (delay, etc.), it is this undesirable feature, limiting the working clock and so on.

Setup Time is the minimum amount of time the data signal should being held steady before the clock event so The data is reliably sampled by the clock. This applies to synchronous input signals to the flip-flop.

hold time is the minimum amount of time the data signal should being held steady after the clock event so T Hat the data is reliably sampled. This applies to synchronous input signals to the flip-flop.

As explained in Wikipedia above, these two concepts are clearly explained, but not specific enough. In other words, there is no mention of how much this value is equal. Xilinx document UG612 Page65 mentions these two equations.

Setup time = Data path Delay + synchronous Element Setup time-clock Path Skew

Hold time = Clock path Skew + synchronous Element hold Time-data path Delay

These two equations tell us that the demand value, the Setup time, is the (minimum) amount of validity required for the data before the rising edge of the clock, and hold time is the (minimum) amount of validity required for the data after the rising edge of the clock. Synchronous element Setup time and synchronous element hold time can be considered as intrinsic properties of the trigger. So, how do you understand these two formulas? Take setup time as an example, hold time has the same nature.

First back to the Wikipedia explanation, which involves the data signal and clock event, what do these two refer to? For a trigger, the settling time for clock_in and Data_in, which is entered directly into its interior, is synchronous Element Setup. This indicates the properties of the trigger. Back to the UG612 definition, which should be used to explain.

Data Signal:d ATA

Clock EVENT:CLK Event

So in this case, the data and the CLK delay arrive inside the trigger, so setup time has changed. There is setup time = Synchronous Element setup time + Data path Delay-clock path Skew

2. How to understand Slack

Talk about a Xilinx company term: Slack. The Chinese meaning of slack is "relaxed" and can be simply understood as the design margin. That is, if the slack is positive, then the design satisfies the requirements, otherwise it does not meet the requirements. For setup time Slack, there are

Slack = requirement-(Data path-clock Path Skew + Clock uncertainty)

Slack = requirement-(clock path Skew + clock uncertainty-data path)

Here Data Path = Data path Delay + synchronous Element Setup time. and clock uncertainty as it literally means, clocks can't be perfect, and the uncertainty of the clock makes slack smaller, which is in line with our perception.

The most notable thing here is that the various ' require ' in the requirement,ug612 have completely knocked me out a few times. The requirement here comes from the constraint, that is, how much of the data in this design can be provided in the time before the clock is valid. The "Data path-clock Path Skew" is actually the setup time mentioned in the previous section, this is a minimum value, if it is greater than the minimum value, then the slack is greater than 0, the corresponding is to meet the requirements. This does not consider the Clock uncertainty,clock uncertainty as shown, the impact is always bad, so the final slack to cut off the value.

is a sequence diagram example, CLK and data correspond to the signals in section 1, clk_in and data_in are the signals that reach the inside of the trigger. The phase relationship between CLK and data indicates that the requirement is a clock cycle. Setup margin is a slack in this example, and the setup margin needs to subtract a clock uncertainty due to clock uncertainties.

Setup time and hold time