Several understandings of Simulink generating HDL

1,simulink generates HDL words need to use a supported module, otherwise cannot be generated, the supported modules form a library, this library needs to build itself, with the Hdllib command generated, the official words:

The Hdllib function creates a library of blocks that is currently supported
For HDL code generation. The Block library, hdlsupported, affords quick
Access to supported blocks. By constructing models using blocks
Library, your models'll be compatible with HDL code generation.

2,simulink generate HDL words need to do some settings, such as the type of solver, in fact, can be done with a command, is Hdlsetup (' model name '), which will be automatically set to generate HDL mode.

3, the model structure of generating HDL is generally subsystem plus testbench, which is similar to the structure of HDL language, generates only HDL files for subsystem, and of course can generate testbench files, HDL can also be generated if the entire model is a function module of HDL, but it cannot be regenerated into testbench.

4, each added module has two properties interface, one is added when the left-click Module two times will come out a parameter settings dialog, there is a HDL block properties, right-click Module, in the Pop-up Properties menu, select hdlcode-"HDL block Properties, there are some HDL optimization options for this module, such as Pipeline,balance delay, DSP style, and so on.

5, HDL can be generated in HDL work flow advisor or directly.

The important triggering and enabling relationships between modules in 6,HDL correspond to trigger in Simulink, enable, input as Boolean, trigger and enable to execute, but not trigger or enable to remain.

Several understandings of Simulink generating HDL