Signal Integrity-Differential Pair Design 3 (simulation difference pair)

To simulate a differential pair, we first need to extract the topology of the difference pair, then simulate it and analyze the simulation results.

(1) Start Allegro PCB Si GXL and open D: \ diffpair \ pci4.brd.

(2) execute analyze-> preferences. The analysis preferences dialog box is displayed.

(3) On the interconnectmodels tab, set percent Manhattan to 100, default impedance to 100ohm, default diff-velocity to 1.4142e + 008 m/s, and select differential Extraction mode.

(4) Click OK to close the dialog box.

(5) execute setup, constraint, and electrical. The Allegro constraint manager window is displayed.

(6) In Allegro constraint manager, select net, routing, and differential pair tables:

(7) In the objects column of the table, right-click dp_loopin and select sigxplorer. The sigxplorer PCB Si GXL window is displayed, showing the differential topology of the ideal coupled transmission line model.

(8) Select the parameters table, and display the circuit in the name column to expand the circuit

(9) Click tlinedelaymode table time, select length, and press tab to change the topology parameter to the length unit.

(10) file-> Save

(11) set simulation parameters and run analyze-preferences in the sigxplorer PCB Si GXL window. The analysis preferences dialog box is displayed.

(12) set pulse stimulus.

(13) set simulation parameters.

(14) set simulation modes.

(15) set measurement modes.

(16) Click OK to disable analysis preferences.

(17) set the differential drive excitation, click the text tristate on u27, And the IO cell (u27) stimulus edit is displayed.

(18) select Custom and change stimulus type to sync.

(19) set frequency to 400 MHz, init to 0, switch at to both, click random, and enter 1024 in the pop-up window.

(20) Click OK to close the dialog box.

(21) execute analyze-> simulate to start simulation. It takes a long time because the pattern length is 1024. The sigwave window is displayed when the simulation is complete.

(22) Run graph-eye dimo-preferences in the sigwave window. The eye dimo-preferences dialog box is displayed. Set clock freq to 400 MHz, no. 1, clock offset is 1/2 clock cycle, that is, 1.25ns, clock start is 0 s.

(23) Click OK and run graph-eye dimo-mode.

(24) Right-click sim1 :... pulse typ reflection, select hide all subitems, all waveforms are not displayed, expand sim1 :... pulse typ reflection, right-click pci4 u37 39_pci4 u37 38_diff and select display.

(25) zoom-specific size, set 0 to 2ns display.

(26) Click Add line:

(27) file-> Save