1. General
is a schematic diagram of the network port structure. The network port consists of three parts: CPU, Mac and PHY. The DMA controller is usually part of the CPU and is placed with a dashed line to indicate that the DMA controller may be involved in the network port data transfer.
For the above three parts, and not necessarily are independent of the chip, according to the combination of forms, can be divided into the following types:
Scenario One: CPU integrated mac and PHY;
Scenario Two: CPU integration mac,phy using independent chip;
Scenario Three: CPU does not integrate Mac with PHY,MAC and PHY using integrated chip;
In this example, the option two is further explained, because the CPU bus interface is very common, usually can be made to access the same as the memory access, no need to come up to say, and the Mii interface between Mac and PHY need to do more explanation.
Is the use of Scheme two network port structure diagram. A dashed box indicates that the CPU,MAC is integrated in the CPU. The PHY chip is connected to the Mac on the CPU via the Mii interface.
The operation of the network port on the software is usually divided into the following steps:
1) Allocate memory for data sending and receiving;
2) initialize the MAC register;
3) Initialize the PHY register (via MIIM);
4) Start sending and receiving;
2 . MII
The Mii interface is the standard interface for Mac and PHY connections. Because the manufacturers adopt the same interface, the user can according to the desired performance, price, the use of different models, and even different company's PHY chip.
The data that needs to be sent is implemented by sending and receiving two sets of buses in the Mii interface. The configuration information of the PHY chip registers is realized through a serial port bus of Mii, namely Miim (Mii Management).
The following table lists some of the main pins in the MII bus
PIN Name |
Direction |
Description |
Txd[0:3] |
Mac to Phy |
Transmit Data |
Txen |
Mac to Phy |
Transmit Enable |
Txclk |
Mac to Phy |
Transmit Clock |
Rxd[0:3] |
Phy to Mac |
Receive Data |
Rxen |
Phy to Mac |
Receive Enable |
Rxclk |
Phy to Mac |
Receive Clock |
Mdc |
Mac to Phy |
Management Data Clock |
MDIO |
Bidirection |
Management Data I/O |
Miim has only two lines, the clock signal MDC and the data line Mdio. Both read and write commands are initiated by the MAC and PHY cannot actively send information to the Mac via Miim. Since MIIM can only be launched by Mac, we can only operate the registers on the Mac.
3. DMA
Sending and receiving data is always a time-consuming effort, especially for network devices. It's obviously inappropriate for the CPU to do these things. Since data is being moved, the simplest way is to let DMA do it. After all, professional is the best.
So the CPU has to do something simple. Just tell the DMA start address and the length, and the rest will be done automatically.
Usually in the Mac there will be a set of registers dedicated users to record the data address, tbase and RBASE,CPU in the format of the Mac to put the data, the start of the MAC data sent is OK. The boot process often uses register tstate.
4. MAC
There are two sets of registers on the CPU with Mac. A group of user data is sent and received, corresponding to the above DMA, a set of user Miim, the user to the PHY configuration.
Both sets of registers are on the CPU and are configured in the same way as the registers on other CPUs, and can be read and written directly.
Data forwarding is done through DMA.
5. PHY
The chip is a 10m/100m Ethernet network-port chip
The PHY chip has a set of registers for the user to save the configuration and update the status. The CPU does not have direct access to this set of registers and can only be accessed indirectly through the MIIM Register group on the Mac.
At the same time, the PHY chip is responsible for transmitting data from the MII bus and media interface. This forwarding is done automatically based on the register configuration and does not require external intervention.
Simple analysis of the principle of Mac and PHY composition