Simple Digital Clock design

Summary of simple digital clock design

In the information age, the concept of time is deeply rooted, so mastering the design of digital clock has certain epoch significance, and using Multisim to design digital clock for discrete components can greatly improve the quality of personal digital circuits.

The design idea is from top to bottom, the first digital clock overall frame design, consider each sub-chip reserved port, and then design each sub-circuit module. Finally, the function of clock display, timing, alarm clock, timekeeping and perpetual calendar is completed. And the total control points reserved the new function of the access port, this way can be very convenient to join the new features.

Directory

Simple Digital clock design ... 1

I. Summary ... 1

Second, pre-preparation ... 2

1, a number of electrical knowledge of the review ... 2

2, Multisim related knowledge of learning ... 2

Three, the circuit general design idea ... 4

Four, sub-circuit design ... 4

1. Control circuit (switching function circuit) ... 4

2, the basic counting function realization: ... 5

3. Clock Timing design ... 10

4. Stopwatch function Design ... 13

5, the fixed-point timekeeping function design ... 14

6. Alarm Clock function design ... 15

7, Perpetual calendar query function: ... 16

8. Display function Design ... 19

Five, experience ... 212, pre-preparation 1, a number of knowledge of the review of electricity

Related knowledge of gate circuit, counter, trigger, 555 trigger and Karnaugh map. 2, Multisim related knowledge of learning

In addition to the basic operations, you should also learn about two large circuit design knowledge. (1) Bus technology:

Figure 2-2-1 Bus Function selection

A, click on the Bus button, and then draw, you can get the bus.

Figure 2-2-2 Bus pattern.

B, double-click the bus to add the bus port:

Figure 2-2-3 Bus port add diagram

C, click Add, you can add the port, there are 2 ways, the first is only one port at a time, the second is the same prefix can be added, but the number of different numbers of ports

Figure 2-2-4 Bus Port mode two add diagram

D, then select the connection confirmation can

Figure 2-2-5 Bus Connection diagram (2) Sub-circuit technology:

A. Create a new sub-module

Figure 2-3-1 Diagram of the method for adding a sub-circuit

B. Add Pins

Figure 2-3-2 Sub-circuit pin add diagram Three, the circuit general design idea

Figure 3-1 Schematic diagram of the total circuit design

First of all the functions of the digital clock: There is a clock display, timing, stopwatch, perpetual calendar, fixed time and alarm clock altogether 6 functions, so the switching circuit to reserve more than 6 function switching items. (Toggle key set to "=")

Secondly, for the digital clock must have a precise second generator as the basis, due to the Multisim itself software refresh frequency problem, so have to use the signal generator as a digital clock of the second generator.

Finally, consider the display function, because only 4 digital tube can be used, so need a display switching function, and then access to the digital tube. (The toggle key is set to "E"). Four, sub-circuit design 1, control circuit (switching function circuit)

Figure 4-1-1 Control circuit construction diagram

(1) The use of the CD4017 10-way 10 beat sequence pulse generator, because there are only 6 functions, so it is changed to six-channel six beat Sequence pulse generator. This also facilitates the expansion of new features.

(2) Select the function by pressing the function toggle button ("=").

(3) The function port is as follows:

Output end	Function
Q0	Clock display
Q1	Clock timing
Q2	Stopwatch
Q3	Alarm clock
Q4	Perpetual calendar
Q5	Fixed-point chime switch

Table 4-1-1 switch Circuit port function table 2, the implementation of the basic counting function:

(1) General conception

Figure 4-2-1 General concept of basic counting function

First of all, according to the actual factors, the use of 8421BCD code to compile, and then according to living habits separated into 7 counters, using on-chip synchronization, inter-chip asynchronous design method.

Second, the week count has two modes, the mode one is used for the normal clock count, that is, 24 hours after the day of the week into one, mode two is the calendar query mode, that is, the need to query the corresponding date of the week when the mode used.

Finally, the port required for the out of tune is reserved.

(2) The design of seconds, minutes and hours Count:

Figure 4-2-2-1 seconds (min) counter design

Figure 4-2-2-2 seconds (min) counter package chip diagram

Port	Function
Q7-q0	Numeric output for access to the digital tube
Cten	Chip selector switch
Cvon	On-chip counter cascade switch
Co	Rounding output
GND	Ground end
Clock0-1	On-chip counter clock end

Table 4-2-2-1 seconds (min) Counter package chip function table

The areas to note are:

A, since the timing function needs to be adjusted for each bit, so each bit must be reserved for the clock end of the timing.

B, because of the on-chip to avoid competition risk and use synchronous cascade, so there must be a cascade switch port (Cvon).

C, due to the time counter and minutes (seconds) counter is only the difference in the system, so no longer detailed description when the counter circuit diagram.

(3) Design of the year counter

In the same way, the design of on-chip synchronization cascade is used to reserve the Cvon and clock0-3 ports required for the adjustment.

Figure 4-2-3-1 The Cascade circuit diagram of the year counter

The reserved ports for leap years are judged for the correct need of day counting.

A, the method of calculating leap year is: can be divisible by 4 and can not be divisible by 100 and divisible by 400 is a leap year.

B, consider using logic circuitry to implement this logic.

① divisible by 400 can be split into 4 and divisible by 100, so the function that needs to be realized is to be able to be divisible by 4 and can be 100.

② can be divisible by 100, as long as the satisfaction of Q0 to Q7 are 0 can be divisible by 100.

The realization that ③ can be divisible by 4:

First, we observe the law of numbers that can be divisible by 4, summed up as:

The 10-bit definition of a number and the number of members are defined as Ab,y=1 to be divisible by 4, y=0 not. Then there are

A	B	Y
Odd	2,6	1
Even	0,4,8	1
Other	0

The rule that the table 4-2-3-1 can be divisible by 4

Then the table table, the Jiancano map, the resulting control circuit is as follows:

Figure 4-2-3-2 can be divisible by 4 circuit diagram

③ judgment can be divisible by 400, first by the ability to be divisible by 100, and set thousands and hundred for A and B, as well as the above law, you can be divisible by 400.

The total circuit of the annual counter is as follows:

Figure 4-2-3-3 Annual counter total circuit diagram and chip package diagram

The annual Counter function table is as follows

Port	Function
Q15-q0	Numeric output for access to the digital tube
Cten	Chip selector switch
Cvon	On-chip counter cascade switch
Vcc	Power side
GND	Ground end
Clock0-3	On-chip counter clock end
Leapyear	Leap Year judgment port

Table 4-2-3-2 Annual count function table

(4) Design of the monthly counter

In the same way, the design of on-chip synchronization cascade is used to reserve the Cvon and clock0-1 ports required for the adjustment.

Figure 4-2-April-January cascade circuit diagram of the counter

A reserved port that has a different number of months is required for the correct day count.

A, count the number of days in different months:

Month	Days
1, 3, 5, 7, 8, 10, 12	31
4, 6, 9, 11	30
2	Leap Year is 29, common year is 28

Table 4-2-4-January days statistics

B, the month by 8421BCD code to compile, through the column Truth table, Carnot diagram simplification, to get the control logic circuit:

Figure 4-2-4-February classification circuit diagram

The total circuit of the monthly counter is as follows:

Figure 4-2-April-March Total counter circuit diagram and chip package diagram

The monthly counter function table is as follows:

Port	Function
Q17-q0	Numeric output for access to the digital tube
Cten	Chip selector switch
Cvon	On-chip counter cascade switch
Vcc	Power side
GND	Ground end
Clock0-3	On-chip counter clock end
Y31	Month with 31 days output is 1
Y30	Month with 30 days output is 1
Y2829	28, 29 Month output is 1

Table 4-2-April-February counter statistics

(5) Design of daily counter

The day counter design idea is the same cascade, but because the number of days per month is different, so we need to use the reserved leap year, y31,y30 and Y2829 port to set the number.

By listing the truth table, the diagram of Carnot is simply the following circuit design:

Figure 4-2-5th counter circuit design diagram

(6) Design of the week Count:

Figure 4-2-6 week counting circuit design diagram

First design a 8421BCD plus counter, choose 0 to 6 as a cycle, which is for the future of the perpetual calendar query convenience.

(7) Basic counting function total circuit:

Figure 4-2-7 Basic counting function total circuit

The point is, how to switch the normal count and adjust, we need to disconnect the original chip selected input clock, instead of manually input clock. Therefore, the Cascade end needs to add a cascade switch, this way you can disconnect the original asynchronous cascade of slices, for manual tuning. 3. Clock timing Design

(1) The idea is summed up:

Figure 4-3-1 Design idea of clock timing

First, you need to make a 11-bit ring counter corresponding to the year, month, day, week, hour, minute and second of each, when a person is "1", when it is adjusted.

Next, is to join the manual adjustment method, need to introduce a button "W", click on the Count plus one.

(2) The realization of the ring counter:

A 11-bit ring shift register is formed using four-piece 741,944-bit shift registers. The circuit diagram is as follows:

Figure 4-3-2-1 11-bit ring shift register circuit design:

How to make one start with one and only one "1" into the effective ring is a key issue. Here is a 2-hour solution:

A, first obtained by 74194 of the function table, when s0=1,s1=1, parallel input, when s0=1,s0=0, move to the right. So we use an integral circuit that causes a short pulse to be entered in parallel when switching to this function.

Figure 4-3-2-2 Integral circuit design:

B, another method is to use an RS trigger.

Figure 4-3-2-3 Parallel input design with RS trigger:

The instantaneous power supply via VCC causes the R port to produce a 1-0 more variable, which, in this way, puts a valid number "1" and then moves to the right shift function.

(3) Manual adjustment function

Take the second digit as an example:

When the Cten (function switch input) is "0", it means that the function is not entered and the Q0 output is a clock signal.

When the Cten (function switching input) is ' 1 ', it means to enter the manual debugging function, the Q0 output is the manual signal. In this case, if the D0 (Ring Shift Register input) is ' 1 ', the pulse generated by the button "W" is allowed to pass through the Q0 output, otherwise it can only be output to low level, i.e., when it is not adjustable.

The remaining bits are also the same connection method.

Figure 4-3-3 Manual Adjustment

(4) Manual adjustment function sub-chip connection

Figure 4-3-4 Manual Adjustment function Sub-chip connection Figure 4, stopwatch function design

(1) General idea of design

First on request "can be timed for marathon running", so need to be able to count up to hours and then select counter Design Hour-minute-second design counter.

Second, you need to reserve a CLR and a stop port for the stopwatch to clear 0 and pause.

Figure 4-4-1 Stopwatch design general idea

(2) Circuit design:

Figure 4-4-2 Stopwatch circuit design Figure 5, the fixed-point timekeeping function design

(1) Design ideas:

Figure 4-5-1 Fixed-point timekeeping function design diagram

According to the requirements, "the time required to chime five short and long, do not need to tell the time", so need to enter some of the clock output to make some logic judgment. Make an output of a high level 59 minutes, 55 seconds to 59 seconds during the time required for the chime, and output a high level in 00 minutes and 00 seconds.

Then it is input to 2 different frequency buzzer, can realize the function of the fixed-point chime.

(2) Circuit design diagram:

Figure 4-5-2 Fixed-point chime circuit lap diagram

Where Cten is the function input, the port on the left is the clock input, switch represents the switching of the fixed-point chime function, and the CIO represents the carry side of the stopwatch. 6. Alarm Clock function design

(1) Design ideas:

Figure 4-6-1 Alarm clock function design idea

First you need to set up a counter to store the setting of the alarm time, make a comparison circuit to compare, if the same words to build a clock ring one minute.

(2) Counting function Construction:

Figure 4-6-2 counting function building diagram

The same as the underlying counter cascade, but made a small change, that is, when adjusting the count, when the 10 bit is 2 o'clock, the digit is only 4 binary counter.

(3) Compare circuit construction:

Figure 4-6-3 Comparison circuit setup

Using the 74ls85 four-bit comparator chip, the clock is compared with the set time, if the same output is "1", the output is "0".

(4) Adjust the set time circuit design:

Figure 4-6-4 Setting time circuit design

It is the same as the circuit that adjusts the always time, but changes the clock switching control built by the tri-State gate to use and the gate to build. 7, Perpetual calendar query function:

(1) Idea design:

Figure 4-7-10,000 calendar query week design ideas

First, each time you enter the calendar to query the weekly function, the current date needs to be imported into the calendar chip, considering the method is not to enter this function, the direct number, one but into this function to turn off the function of the terminal.

Second, the query is divided into 3 minutes, adjust the day, adjust the month, adjust the year, in the corresponding adjustment, the week to make corresponding changes.

Finally, the matching output of the display function should be added.

(2) Year query design:

First set up a year counter, directly reuse the original clock used in the year counter, and then add a year as an example:

A, analysis of the situation:

Case	Results
The corresponding date of the leap year to common year after March 1	Week plus One
The corresponding date of the leap year to common year before March 1	Week plus Two
The corresponding date of common year to leap year after March 1	Week plus Two
Common year date to leap year before March 1	Week plus One
Common year to common year corresponding date	Week plus One

Table 4-7-2 Annual corresponding Week rule summary

B, through the Carnot diagram simplification, you can get the circuit design:

Figure 4-7-2 Design circuit diagram for the corresponding week

Even with an accelerometer, through the control circuit, control in different cases, the B4B3B2B1 port corresponds to a value.

(3) Month Correspondence date query

First set up a one-month counter, directly reuse the original clock used in the monthly counter, and then add one months as an example:

A, analysis of the situation:

Case	Results
Last month was 31 days.	Plus 3 days
Last month was 30 days.	Plus 2 days
Last month was 29 days.	Plus 1 days
Last month was 28 days.	Plus 0 days
Jump from December to January (same 31 days)	Plus 3 days

Table 4-July-March corresponding Week rule summary

B, through the Carnot diagram simplification, you can get the circuit design as follows:

Figure 4-7-March corresponding week query circuit query design

(4) Date query:

First build a daily counter, directly reuse the original clock used in the day counter, and then add a day as an example:

A, analysis of the situation:

Classification	Case	Results
Jump from number 31st to number 1th.	Last month was 31 days.	Plus 2 days
Last month was 30 days.	Plus 1 days
Last month was 29 days.	Plus 0 days
Last month was 28 days.	Plus 6 days
Other	Plus one day	Plus 1 days

Table 4-7-4 days corresponding weekly query rule summary

B, through the Carnot diagram of the simplified circuit design diagram is as follows:

Figure 4-7-4th corresponding week query circuit design diagram

(5) 3 Ways to change the query:

First, the same as the circuit, need to have the corresponding adjustment toggle button, and also need to select the results of the operation output:

Figure 4-7-5 The result of the operation output circuit design diagram

Select the value of the output, and if it exceeds 6, the operation is reduced by 7. Ensure that the output of the week is 0 to 6 (from Monday to Sunday).

(6) Threshold switch:

Figure 4-7-6 Valve value Switch design diagram

If you do not add a threshold switch, it will form a closed loop, turn into a ring counter, but we can be a counter to make a switch, when the end of the set is opened, the output will not proceed, otherwise it will not continue to output. The opening of the terminal is obtained by the pulse triggered by the button at the time of the adjustment. 8. Display function Design

Figure 4-8-1 Display function Preview diagram

(1) Display function and design idea

Figure 4-7-1-2 Display function Introduction diagram

A, the upper left corner: Indicates the alarm clock and the point chime switch, the light indicates that there is open, otherwise it is not opened.

B, above: In the clock display and adjust the function, the digital tube displays the content is:

1: Show minutes and seconds

2: Time and minute

3: Mean month and day

4: Mean year and month

C, right: Indicates the function selection, which light illuminates which function.

D, Middle: digital, direct display of numbers

E, below: Week output, the day of the week is which one light on

(2) Toggle display function

A: Analysis:

Since there are only 4 digital tubes, it is necessary to choose the output of the data, it is obvious that the data selector should be used, and the 74as157n can be used for data selection.

B: As an example, the switching between days and seconds is as follows:

Figure 4-7-2 Month Day time seconds function Select output

Left box: Another sequential pulse generator, which outputs different pulses when the button is pressed. We program the control end of the data selection by the output of the different routes sold.

The above box: three-state gate, the control end for the corresponding function switching circuit enable, indicating that only in the current function, will output the data in this chip, it means that each need to connect the sub-circuit of the digital tube need to have this circuit.

Data set selection circuit: mainly using the output of sequential pulse generator programming, the data selector to program, this way you can choose to output the corresponding desired value.

(3) The flashing function of the time-modulation:

Figure 4-7-3 Power-on-time bit flicker function circuit design diagram

A, first determine the need to blink the bit to meet the conditions:

① must be displayed on the current page

The output of the sequential pulse generator used in the ② adjustment is valid

③ Enter the Adjust-time function option

B, therefore, the sub-block to complete the corresponding function

From bottom to top, respectively, 1,2,3,4 module

Module one: corresponding to the proposed function of a logic circuit designed to act as the control side of module two

Module two: When the input control end is 1, the output flashing signal, otherwise the output does not blink signal (ground).

Module three: When the clock display function in any case does not blink, only under the debugging function to blink.

Module Four: The output will only be available if you enter this function. Five, experience

1, more profound and more proficient in the design of digital electrical technology, master a variety of basic circuits, such as counters, triggers, registers, 555 and single-stable multi-harmonic and so the sum of the use of knowledge.

2, clever use of calculus circuit, you can create a required pulse, simplify the circuit.

3, all the simulation has ignored the actual device parameters, in fact, many places need to add resistors, capacitors, this way can make the circuit normal work, such as seven segment of the digital tube, the input port needs to add resistance, otherwise flicker is not synchronized.

4, the limitations of Multisim software is very large, the refresh frequency is not large enough, each change to fully iterate over the array, so unscientific method really makes large circuit design difficult to carry out. But when we have no way to change the rules, we have to make our own compromises:

(1) Each sub-circuit is designed in a new design, this does not create the problem of the connection.

(2) When the logical function is not produced corresponding effect, such as carry, this is because the parameters of the device does not match, but the Multisim will not be an error prompt, we need to solve, one is to add a resistor capacitor to match, another method is to add the probe, it will be self-matching.

(3) When the port connection, try to connect as many ports as possible, because traversing an array once can be all added. So it must be so.

5, design the circuit when the best idea, from top to bottom macro layout, bottom modify the layout. And then repeated several times, confirm the idea is feasible, start from the foundation, reserved port. Do your notes.

6, circuit design is a time-consuming thing, we need to discuss together, everyone's ideas are different, we discuss, improve each other, finally will make efficiency improvement.

Simple Digital Clock design