Simple implementation of 3_8 decoder Verilog HDL language

Recently learning Verilog HDL language, think learn in doing is a better way to learn, so we have to directly analyze and analyze the code well.

First a wave of code:

1 Moduleq_decode_38 (data_in,data_out);2       3         input[2:0] data_in;//Port Declaration4         Output[7:0] Data_out; 5         Reg[7:0] Data_out;6          7  always@ (data_in)8    begin 9          Case(data_in)Ten                  3'd0:data_out = 8'b0000_0001; One                  3'd1:data_out = 8'b0000_0010; A                  3'd2:data_out = 8'b0000_0100; -                  3'd3:data_out = 8'b0000_1000; -                  3'd4:data_out = 8'b0001_0000; the                  3'd5:data_out = 8'b0010_0000; -                  3'd6:data_out = 8'b0100_0000; -                  3'd7:data_out = 8'b1000_0000; -          Endcase +      End -       + Endmodule

The code analysis is as follows:

Knowledge Points:

(1) Basic statement

1) Conditional Statement---Case statement

The case statement is obvious, and the format is similar to the C language and is not explained. It is worth noting that the above code is not the case of defaule? This omission is due to the fact that all the cases are listed, but it is generally not recommended to omit them, because it is easy to generate unnecessary latches if there is an unknown situation.

2) Sequential block statement---begin...end statement

The Begin...end statement has no special requirements, that is, the statement between the order block Begin...end is executed from top to bottom, from left to right.

3) PROCEDURE Statement---always statement

The format of the always statement is [email protected] () followed by the Begin...end statement, in parentheses is the trigger condition, the above code indicates that as long as the value of data_in changes, the begin...end part of the always after the execution, otherwise not executed.

(2) Basic ability to achieve

This is a relatively simple 3-8 decoder circuit program, the specific function will not say, but this can be downloaded to the FPGA board to observe, for example, can be three dial switch control 8 LED lights to observe the dialing switch and LED light State contact.

Simple implementation of 3_8 decoder Verilog HDL language