Computer Systems A Programmer ' s perspective Second Edition
Many computer systems place restrictions on the allowable addresses for the
Primitive data types, requiring, the address for some type of object must being amultiple of some value K (typically 2, 4 , or 8). Such Alignment Restrictions Simplifythe design of the hardware forming the interface between the processor and Thememory s Ystem. For example, suppose a processor all fetches 8 bytes frommemory with an address that must be a multiple of 8. If we can guarantee that anydouble would be aligned to has its address is a multiple of 8, then the value canbe read or WR Itten with a single memory operation. Otherwise, we may need to perform of the memory accesses, since the object might be split across and 8-bytememory blocks . linux follows an alignment policy where 2-byte data types (E.g.,short) must has an address so is a multiple of 2 , while any larger data types (E.g.,int,int *,float, and double) must has an address, which is a multiple of 4.Note that thi s requirement means that the least significant bit of the address Ofan object of type short must equal Zero. Similarly, any object of type int, or anypointer, must is at an address has the Low-order 2 bits equal to Zero. mi Crosoft Windows imposes a stronger alignment requirement-any primitive object OfK bytes, for k=2, 4, or 8, must has an ad Dress is a multiple of K. In particular,it requires, the address of a double or a long long be a multiple of 8. Thisrequirement enhances the memory performance at the expense of some wasted space. The Linux convention, where 8-byte values is aligned on 4-byte boundaries is probablygood for the i386, back when memory Was scarce and memory interfaces wereonly 4 bytes wide. With modern processors, Microsoft's alignment is a better design decision. Data type long double, for which GCC generates IA32 code allocating bytes (even thoughthe actual data type requires ONL Y bytes) has a 4-byte alignment requirement Withboth Windows and Linux.
Simplify the design of the hardware forming the interface between the processor and Thememory system