Single and multiple launches

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Pipeline Technology: A quasi-parallel processing technology that allows you to execute multiple commands at the time of execution. The assembly line was first used by intel in the 486 chip. The pipeline works like an assembly line in industrial production. In the CPU, a command processing pipeline is composed of 5-6 circuit units with different functions. Then, an x86 command is divided into 5-6 steps and then executed separately by these circuit units, in this way, an instruction can be completed in a CPU clock cycle, thus improving the computing speed of the CPU. Each integer assembly line of the classic Pentium is divided into four levels of flow, namely, command prefetch, decoding, execution, and write-back results. The floating point flow is also divided into eight levels of flow.

2. throughput: refers to the number of tasks or output data results that can be processed by a computer pipeline at a specific time. The pipeline throughput can be further divided into the maximum throughput and the actual throughput. They are mainly related to the processing time of the stream segment and the delay time of the cache register. The longer the processing time of the stream segment, the longer the delay time of the cache register, the throughput of this pipeline is smaller. Because, in a linear pipeline, the maximum throughput is tpmax = the clock cycle of the pipeline △t/1 = max (T1 ,... ti ,.. TM) + t1/1, where M is the number of segments in the pipeline, and I is the execution time of specific process segments. If the number of segments in a pipeline increases and the execution time is longer, the theoretical throughput of the pipeline decreases.

3 single and multiple launches

The instruction execution of a single transmitting processor extracts only one instruction from the memory within a clock period, decodes only one instruction, executes only one instruction, and writes only one operation result.
In a single-emission processor, only one set of instruction component and Instruction Decoding component is set. The operating component can be set to only one multi-function operation component, or multiple independent operation components. For example, Alu, LSU, FAD, and mdu. A single-emission processor generally uses a pipeline structure at the command level. In the operating components, some machines use the pipeline structure, and some machines do not use the pipeline structure.
The single-emission processor is designed to execute an average instruction per clock cycle, that is, it has an expected value of 1 for its instruction-level concurrency ILP. In fact, it is a common scalar processing machine with K-segment pipelines. Because of data correlation, conditional transfer, and resource conflicts, the actual ILP cannot reach 1. By optimizing the compiler to reorganize the instruction sequence (recorganizer), and using a combination of software and hardware to process data-related, conditional transfer, and resource conflicts, we can make ILP close to 1. However, the ILP of a single transmitter cannot be greater than 1.

Figure empty execution time of commands for single-launch and multi-launch Processors

The multi-transmitter reads multiple commands from the instruction cache at the same time within a basic clock period and decodes multiple commands at the same time. To enable multiple sending commands at the same time in a clock cycle, multiple command receiving components, multiple command decoding components, and multiple Write result components are usually required.

4 SIMD :( Single Instruction Multiple Data, single command multiple data streams) can copy multiple operands and package them into a set of instruction sets of large registers.

Execute the same command at the same time in synchronous mode.

Taking the addition command as an example, after the CPU of a single command and single data (sisd) decodes the addition command, the execution part first accesses the memory to obtain the first operand, and then accesses the memory again, obtain the second operand before performing the sum operation. In a SIMD-type CPU, several execution components after Instruction Decoding access the memory at the same time to obtain all the operands for calculation at a time. This feature makes SIMD especially suitable for data-intensive operations such as multimedia applications.

MIMD :( multipleinstructionstreammultipledatastream multi-instruction multi-data stream), it uses multiple controllers to asynchronously control multiple processors, so as to achieve space concurrency.