Single-chip computer test questions

1 , the bits defined in the bit address area in internal ram are given (B).

A). bit operation preparation B). (C) to be prepared for the shift operation). To control transfer operation preparation D). All of the above
2 , the operation of the program counter PC (A).

A). is automatically carried out B). It's through the transmission.

C). Is through the addition of 1 instructions D). It was done by minus 1.

3 , Assuming that the value of the set stack pointer sp is 37H, the SP has a value of (D) after the breakpoint address is stack protected when the subroutine is called.
A). 36H B). 37H C). 38H D). 39H
4 , in the Operation Circuit of the MCS-51 MCU, the data of the ALU can not be provided (D).
a). Accumulator a B). Scratchpad C). General Register B D). Status Condition Register PSW
5 , the external interrupt signal of the edge triggering mode is (A) valid.

A). Falling Edge B). Rising edge C). High level D). Low Level

6 , MCS-51 when the response is interrupted, which one of the following conditions is not required (B).

A). The execution of the current instruction is complete B). Interrupts are open

C). No sibling or advanced Interrupt service D). Must have a RETI directive

7 , The register that determines how the timer/counter works is (B).

A). TCON B). Tmod C). SCON D). PCON

8 , asynchronous serial communication, both the transceiver and the receiver must remain (B).

A). Transceiver Clock same B). Stop bit Same

C). The data format is the same as the baud rate D). The above are correct

9 , the top position of the accumulator is 1, the remaining bits are unchanged, and can be implemented with the following (A) instruction.

a). ORL A, #80H B). ANL A, #80H

C). XRL A, #80H D). MOV A, #80H

Ten , when the memory chip is extended outside the MCS-51 microcontroller, the 4 I/O ports are used as address bus (B).

A). P0 Port B). P0 and P2 Port C). P2 and P3 D). P2 Mouth

One , the signal that does not work when accessing the external data memory is (C).

A). RD B). WR C). PSEN D). ALE

A , in the following instruction, the instruction belonging to the simple Read PIN is (C).

a). MOV P1, a B). ORL P1, #0FH

C). DJNZ P1, LAB D). MOV C, P1.5

- , The read operation of the program memory can only use the (C) instruction.

A). MOVX B). PUSH C). MOVC D). MOV

- , If the MCS-51 interrupt source is programmed to be siblings, when they simultaneously request an interrupt, the CPU begins with the corresponding (B)

A). INT1 B). INT0 C). T1 D). T0

the , when the MCS-51 for multi-machine communication, the serial interface should be selected as the mode of operation (D)

A). Mode 0 B). Mode 1 C). Mode 2 D). Mode 2 or Mode 3

1 , When RS1 rs0=10h is in the PSW, the address of R2 is 12H.

2 , MCU after power-on reset, the address of the first instruction is 0000H.

3 , in serial communication, the data transmission direction has simplex, half-duplex, full duplex three ways.

4 , one machine cycle = 6 status cycles = 12 oscillation cycles.

5 , set dptr=2000h, (A) =a0h, the actual operating address of the MOVC a,@a+dptr operand is 20a0h.

6 , if the 8051 MCU pin EA grounding, indicating only to access the off-chip program memory.

7 , in the MCS-51 single-chip microcomputer system, the address method used is a unified address.

8 , in the query and interrupt two kinds of data input and output methods, the more efficient is the interruption.

9 , instruction Lcall 37b0h, the first address in 2000H, the completion of the operation is 2003H into the stack, pc= 37b0h.

Ten , External interrupt INT1 entry address is 0013H.

One , ANL A, #0F0H是将A的高四位保持不变, and A low 4-bit inversion.

A ,8051 single chip microcomputer Timer/counter for timing and counting time, its counting pulse by 8051 internal pulses and P3.4 or P3.5 pin end of the external

Pulses provided by the department.

Judge the right and wrong of the following statements, hit "√", "X", and correct the wrong narrative.

1                                     , The reset is the initialization operation of the monolithic microcomputer. √

2  , the bit addressing area of internal RAM, which can only be used for bit addressing and not for byte addressing. (x) can be byte addressed

3                  , in the relative addressing method, the result of addressing is embodied in the dptr. (x) PC

4 ,                       The PC stores the address of the instruction that is currently executing. (x) Next Decree address

5 , mov 28H, @R4 (x) mov 28H, @R0 or mov 28H, @R1

1 ,(4 points) briefly describes the principle of single-chip microcomputer processing of interrupt priority.

A: 1) first handle high-priority interrupts, and then handle low-priority interrupts

2) If these interrupts are of the same priority, they are queued in the order of the interrupted hardware query, processed sequentially

3) If a low-priority interrupt is currently being processed, it can be interrupted by another high-priority interrupt, resulting in an interrupt nesting, if the CPU is interrupted.

4) If a high-priority interrupt is currently being processed, no other interrupts are temporarily in response.

2 ,(6 points) 8051 MCU what kinds of addressing methods? Each addressing method involves which registers and memory space. Please state.

For:

Addressing mode	Registers involved	The storage space used
Direct addressing		On-chip RAM low 128-bit byte
Register addressing	R0~r7,a,b,cy,dptr	In-Chip RAM
Register Indirect Addressing	R0,r1,dptr	On-Chip RAM, off-chip RAM and I/O ports
Immediate number addressing		Program Memory
Base register plus variable address register indirect addressing	A,pc,dptr	Program Memory
Relative addressing	Pc	Program Memory
Bit addressing	Cy	On-Chip Ram 20H~2FH, part SFR

1 ,(5 points) programming to achieve the following operations: Set di as the corresponding bit in the on-chip Ram 22H Unit, the result of the operation is stored in the Carry bit CY.

MOV c,22h.0

ANL C,22h.1

MOV 22h.2,c;D 0.d1->d2

CPL 22h.1

MOV c,22h.0

ANL c,22h.1;D 0.d1_->c

ORL c,22h.2;D 0.d1+d0. D1_->c

CPL C

MOV 22h.2,c

MOV c,22h.7

CPL C

ANL c,22h.5;D 5.d7_->c

ORL c,22h.2

2 ,(5 points) try to write the sub-program of delay 2S, and give the calculation of 2S time.

ORG 000BH; T0 Interrupt Entry

AJMP BRT0; jump to BRT0 execute Interrupt Service Program

DELAY: MOV Tmod, #01H; set T0 for timing, Mode 1 way

MOV TH0, #3CH; loading timing initial value

MOV TL0, #0B0H

MOV IE, #82H; T0 allow interrupts

Setb TR0; start T0 count

MOV R0, #14H; software counter R0 assignment value

LOOP: SJMP $; Wait for interrupt

BRT0: DJNZ R0,next; if not to 1s, go to NEXT

RET; This delay subroutine returns

NEXT: MOV TH0, #3CH; reload Timer initial value

MOV TL0, #0B0H

RETI

1 ,(9 points) using SRAM chip 6264 extended 8KB data memory (hint: 6264 There are two chip-select signals CE1, CE2). Try ① to determine the address decoding range, write out all possible address ranges, ② draw the system structure diagram.

A: (1) due to the CE1 (active low) grounding, CE2 (active high) as a chip selection, then P2.7, so its address range is 1xx0 0000 0000 0000b~1xx1 1111 1111 1111B

Possible address decoding range: 8000H~9FFFH,A000H~BFFFH,C000H~DFFFH,E000H~FFFFH

2)

2 ,(16 points) the connection between MCS-51 and ADC0809 as shown, the A/D conversion results are stored in the off-chip data memory 40h~47h unit, and the data transfer address register of MCU and A/D converter is dptr. ① try to determine the channel address, ② trial interrupt mode to write A/D converter interface program and write out comments.

(1) 78h~7fh

(2)

ORG 0000H

START: AJMP MAIN

ORG 0003H

AJMP EXINT0

ORG 0030H; Indicates that the main program starts with a 0030H address

MAIN: MOV R0, #40H; the first address where the sampled data is stored

MOV R1, #78H; IN0 Channel location

MOV R2, #08H; analog channel number

MOVX @R1, A; start A/D conversion

SETB IT0; external interrupt 0 is the Edge trigger mode

SETB EX0; Allow external interrupt 0 interrupt

SETB EA; open CPU Interrupt

Here : SJMP here

EXINF0: PUSH PSW Protection site

CLR RS0

CLSR RS1

MOVX A, @R1; Read conversion results

MOV @R0, A; Storage results

INC R0

INC R1

DJNZ R2,next; 8 channel not finished, then take the next channel

CLR EX0; After acquisition, stop interrupt

SJMP Done

NEXT: MOVX @R1, A; start the next channel A/D conversion

Done : POP PSW

RETI

END

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Single-chip computer test questions