Soft interrupts and hard interrupts

Source: Internet
Author: User

1. Interruption:
is typically defined as an event that alters the order of instructions performed by the processor. Such events are generated with the external circuitry of the CPU chip
corresponding to the electrical signal.
2, the production of interrupts:
Each hardware device controller that can make an interrupt request has an output line called an IRQ (middle wire break). All the IRQ lines are
connected to the input pin of an interrupt controller, the interrupt controller is connected to the INTR pin of the CPU.
3. Interrupt vector:
Each interrupt is identified by a 8-digit number between 0-255. called the interrupt vector.
4. Interrupt Descriptor Descriptor:
IDT is a system table that is associated with each broken or anomalous vector, with each vector having a corresponding interrupt process in the table
The entry address of the sequence. The IDTR register of the CPU executes the physical base address of the IDT table.
5. Interrupt Hardware Processing:
After the kernel is initialized by the INIT process, the CPU is running in protected mode. When executing an instruction, SC and EIP this pair of register packets
Contains the logical address of the next instruction that will be executed. Before executing this instruction, the CPU control unit checks that the previous instruction is run
No interruption occurred. If this occurs, the CPU control unit handles the interrupt.

Soft Interrupt:

Soft interrupt is the concept of hardware interruption, which is simulated by software to realize the effect of asynchronous execution on macro.
A hard interrupt is an external device interrupt to the CPU.
Soft interrupts are usually interrupts to the kernel by the hard Interrupt service program. (Interrupt service program and interrupt handler are different)
Signals are interrupts by the kernel or other processes to a process.
Understanding: Because each process space or thread space is somewhat relatively logically independent, similar to the external device DMA phase
For CPUs. So theoretically, it is possible to achieve disruption.
Extensions: semaphores and Message Queuing are both provided to the user program and are a encapsulation of the kernel service.

Process kernel stacks and user stacks:
Each process has two stacks: a user stack and a kernel stack. When the process is running in user space, the inside of the CPU stack pointer register
is the user stack address. In the same vein, when the process runs in kernel space, the EIP value is the kernel stack space address.
The process user stack and the kernel stack switch, when the process because of the interruption or system calls into the kernel state execution, the process used by the
The stack also goes from the user stack to the kernel stack.
Check that the signal is interrupted when the kernel state is about to enter the user state, not at any time.
Soft interrupt when the software implementation of the interruption, that is, the program is running when other programs interrupt it.
After interrupting the source interrupt request or the soft interrupt signal, the CPU or receiving process automatically interrupts processing or completes at the appropriate time.
The function of the soft interrupt signal.
The time the soft interrupt occurs is controlled by the program, while the hard interrupt is random.
The core element that forms the soft interrupt mechanism:
Soft Interrupt status Register Irq_stat:
Soft Interrupt vector table:
Soft Interrupt Daemon Daemon: This is the core of the soft interrupt implementation, and the query Irq_stat to determine whether the soft interrupt occurs.
The soft interrupt work process simulates the hard interrupt process, and when a soft interrupt event occurs, the first one needs to set the corresponding interrupt mark
A bit, triggering an interrupt transaction, and then waking the daemon to check the interrupt status register, if the query finds a soft interrupt transaction to occur,
Then the soft interrupt Service program action is invoked through the soft interrupt vector table.

Soft interrupts and hard interrupts (RPM)

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