ARM assembly instructions are many, but the real use is not a lot, but also need to seriously think about less. More useful is MOV B BL LDR STR or through the specific assembly code to learn it.
@ Disable Watch dog timer
mov r1, #0x53000000//
immediate number addressing mode
mov r2, #0x0
str R2, [R1]MOV There is nothing to say, as long as the master a few ways to address, and ARM to address the way is much simpler than 386. Immediate number addressing mode,
the number immediately requires the
#
"
as a prefix, and for hexadecimal numbers, it also requires the
#
add it back .
0x
or
&。 0x everyone understands it very well. One time I came across the number of &ff, and now I understand that 0xFF is the same. STR is a more important instruction, and it corresponds to LDR. The ARM instruction set is loaded/stored, which means it only processes data in registers. Then the access to system memory is often used for STR and LDR. STR is the transfer of data from the registers to the storage at the specified address. Its format I personally think is very Special: STR (conditional) source register, < memory address > such as str R0, [R1], meaning r0-> [R1], it writes the source registers in front, with MOV, LDR are the opposite. LDR should be very common. LDR is the transfer of data from memory to registers. and a pseudo directive is also LDR, so I have a puzzled question. Look at this code:
mov r1, #GPIO_CTL_BASE
add R1, R1, #oGPIO_F
LDR R2,=0X55AA//0X55AA
is an immediate number Ah, the front plus a = what to do.
str R2, [R1, #oGPIO_CON]
mov r2, #0xff
str R2, [R1, #oGPIO_UP]
mov r2, #0x00
str R2, [R1, #oGPIO_DAT]For the ldr of the sentence, I do not understand, if you take = removed, is not compiled. I checked some information, and I know why.
: The
=
should indicate
LDR
is not
ARM
directives, but pseudo directives. As a pseudo instruction, the LDR format is as follows: LDR register, = numeric constant/label its function is to transfer a 32-bit address or a constant to the register. Ho ho, then you may ask, "MOV R2, #0x55aa" can also ah. That should be the case. However, LDR is a pseudo directive, which means that the compiler will handle it at compile time. How to deal with it. The rules are as follows: If the numeric constant is within the MOV instruction range, the assembler will take this instruction as Mov. If it is not in the MOV range, the assembler puts the constant behind the program, reads it with LDR, and the PC and the constant cannot be offset more than 4KB. That said, although indefinitely, but can explain this statement. Then say the jump instructions. ARM has two ways to jump. (1) MOV pc < jump address this to the program counter PC Direct write jump address, can in 4GB continuous space any jump. (2) through B BL BLX BX can be completed in the current instruction forward or back 32MB address space jump (why 32MB it. The register is 32-bit, at which point the value is 24-bit signed, so 32MB). B is the simplest jump instruction. Note that the actual value of the jump instruction is not an absolute address, but a relative address--is an offset from the current PC value, and its value is computed by the assembler. BL is very often used. It saves the current contents of the PC in Register LR (R14) before jumping. The classic use of BL is as follows:
BL NEXT;
Jump to next
.....
NEXT
.....
mov pc, LR;
returns from a subroutine. Finally, mention the THUMB instructions. The ARM architecture also supports a 16-bit Thumb instruction set. Thumb instruction set is a subset of ARM instruction set, it retains the advantage of 32-bit code while saving storage space greatly. Because the Thumb instruction set is only 16 bits long, its instructions are more numerous. It and ARM each have their own application occasions. For system performance, 32-bit storage system and arm instruction set should be used, and 16-bit storage system and arm instruction set should be used for the higher requirements of cost and power consumption.
The understanding of ARM anomaly (exceptions)Category: Technical notes
BI Set notes
1
. Right
ARM
Exception (
Exceptions
) of understandingAll of the system bootstrapper will have a similar code in front of it, as follows:
| . Globl _start system Reset Position _start:b reset jump codes corresponding to each anomaly vector ldr PC, _undefined_instruction; undefined instruction exception ldr PC, _software_interrupt software interrupt exception ldr pc, _prefetch_abort , memory operation exception ldr pc, _data_abort Data Exception ldr PC, _NOT_USED&NBSP;&NBSP;&NBSP;&NBSP;&NBSP;&NBSP;&NBSP;&NBSP;&NBSP;&NBSP;&NBSP;&NBSP;&NBSP;&NBsp; ldr pc not used, _irq Slow Interrupt exception ldr pc, _fiq Fast Interrupt exception |
From this we can see that ARM supports 7 kinds of exceptions. How does ARM respond when an exception occurs? The first reset exception is well understood, it is placed in the 0x0 position, it is executed as soon as the power is on, and our program is always executed from the reset exception handler, so the reset exception handler does not need to be returned. So how do you perform to the following exception handlers? After reading the book, understand the ARM of the exception response process, so can answer the previous question. When an exception occurs, ARM automatically performs the following steps: (1) Placing the address of the next instruction in the connection register LR (usually R14) so that it can proceed from the correct position when handling the exception return. (2) Copy the corresponding CPSR (the current program status register) to the SPSR (the Backup program status register). When you exit from an exception, you can restore the CPSR by SPSR. (3) According to the type of exception, the CPSR is forced to set the running mode bit. (4) Force the PC (program counter) to remove the next instruction from the relevant exception vector address, and then jump to the corresponding exception handler. I did not delve into what these types of anomalies represented. Because the usual care about reset, there is no need to find out. ARM sets the address of the anomaly vector: b reset resetting 0x0 ldr pc, _undefined_instruction; undefined instruction exception 0x4 ldr pc, _software_interrupt software interrupt exception 0x8 ldr pc, _prefetch_abort pre-fetch instruction 0xc &NBSP;&NBSP;&NBsp; ldr pc, _data_abort Data 0x10 ldr pc, _not_used not used 0x14 ldr pc, _irq Slow Interrupt exception 0x18 ldr pc, _fiq Fast Interrupt Exception 0x1c This is a very simple way to understand this piece of code. When an exception is encountered, the PC is forced to set the corresponding exception vector, which jumps to the appropriate handler and then returns to the main program to continue execution. The interrupt vectors for these bootstrapper are for the bootstrapper to use only, and once the bootstrapper has booted the Linux kernel, it will use its own interrupt vector. Ho-ho, that's a problem again. For example, when arm interrupts (IRQ), it always runs to the 0x18 to execute AH. How can the Linux kernel use its own interrupt vector? The reason is that the Linux kernel uses page storage management. After opening the MMU page map,
the address that the CPU emits is the virtual address, not the physical address.。 As far as the Linux kernel is concerned, the physical address of the virtual address 0x18 after mapping is 0xc000 0018. So Linux puts the interrupt vector on the 0xc000 0018. Also, say something about MMU. To tell the truth, the MMU mechanism is not quite clear yet. While attending Intel training, Li Yu said the two main roles of MMU: (1) Security: Specify access Rights (2) Provide address space: The discontinuous space is converted to continuous. The 2nd is to realize the meaning of the page-type storage. June 9, 2005 evening Add: 05/06/14
. globl _start; system Reset Position
_start:b reset; jump codes corresponding to each exception vector
Ldr pc, _undefined_instruction; undefined instruction exception
......
_undefined_instruction:
. Word undefined_instruction
Perhaps some people will have the question, also is the jump instruction, why the first sentence uses is B reset;
And a few of the following are used Ldr.
To understand this problem, we take an undefined instruction exception as an example.
When this exception occurs, the CPU always jumps to 0x4, which is the virtual address and which physical address it maps to.
Depends on the specific mapping.
Ldr pc, _undefined_instruction
Relative addressing, jump to the label _undefined_instruction, but the real jump address is actually _undefined_instruction content--undefined_instruction. The word is equivalent to:
_undefined_instruction DW Undefined_instruction (see note 3).
This address undefined_instruction in the end how far is difficult to say, perhaps and the label _undefined_instruction on the same page, perhaps in a very far place. However, except reset, the other exception is that MMU began to work before it could happen, so Undefined_instruction's address also passed MMU mapping.
When the electricity was just added, the CPU starts from the 0x0, the MMU has not yet started to work, the virtual address and physical address are the same at this time, on the other hand, the restart is also possible after MMU start work, if reset also use LDR has a problem, because the virtual address and physical address is completely different.
Therefore, the reason to reset with B, is because reset in the MMU before and after the establishment of the possible, and other exceptions only after the establishment of MMU will occur. With b Reset,reset subroutine and reset vector on the same page, so there will be no problem (b is relative to jump). If the two are too far apart, the compiler will complain. Http://blogold.chinaunix.net/u2/62218/showart_486059.html
