Some understandings of FPGA timing analysis

At the beginning of some of the information, we actually talk about the same, but I see foggy, should be not really understand this thing.

Today, the whim of the "seven days to play turn Altrea time series" took out to see, should have some enlightened feeling, in the next is stupid, want to understand a thing too slow.

First look at the register-to-register path, 1:

Data arrive time: the date when the reg2.d is reached. When timing analysis is performed, the data arrive time calculation formula is the same for setup and hold.

The understanding of data arrive time is based on the first register REG1, which is independent of Register 2 (REG2), and REG1 is the register that initiates the data transfer.

when the data can reach REG2. D is the D input of trigger 2, mainly by the REG1 and the middle of the combinatorial logic comb, this time t=tclk1+tco+tdata, because the register after the logic is fixed, so

This time is fixed as long as there is data transfer initiated by this register. The CLK rising edge at which data transmission originated is lanch, then data arrive time=lanch+tclk1+tco+tdata, such as.

In short, the above sentence is summed up as follows:data arrive time is the initiator (source) Register REG1 based on the analysis. The first rising edge of CLK starts this data transfer from the rising edge to the time when the data reaches reg2.d. That is data arrive time.

Some understandings of FPGA timing analysis