Sparse SPI interface IP

Reference http://www.fpga4fun.com/SPI2.html

 

CLK is a 50 m crystal oscillator of FPGA

To use the four-wire SPI mode, the SSEL signal must be available. 8-bit data mode, polarity = 0, phase = 1.

 

Send data:

Send the data to byte_data_tosent, and byte_sent_request provides a rising edge, so that byte_sent_int also gives the DSP a rising edge, triggering dsp spi reading.

 

Receive data:

When byte_received generates a rising edge, it indicates that the byte_data_received data is valid and can be read.

 

 

Simulation waveform:

The sent data is 0xf1, And the received data is 0xfa.

 

: Http://download.csdn.net/source/2352199