Spartan-3e starter kit board getting started

This article briefly introduces 4 slide switches and 8 LED lights on spartan-3e starter kit board via Ise.

 

I. Design Ideas

1. One end of the LED light on the board has been connected to a low level. Therefore, to light it up, you need to output a high level to the other end.

2. The 50 MHz crystal oscillator and reset keys on the board are the input of the design module. In order to respond to the input in step 3 in a timely manner.

Sw2, SW1, and sw0 in the 3 and 4 slide switches serve as another group of inputs.

4. the encoding of sw2, SW1, and sw0 is the LED lamp to be lit. That is, if it is set to, led0 is lit, = 001, and led1 is lit.

 

2. Create a project from ISE and finally download. Bit to the board.

1. Fire-> new project

2. The chip model and encapsulation must be selected.

3,

4. Right-click the project management area, select new source, select the OpenGL module, and enter the fire name.

5. Set the input and output ports of the module.

6,

7. Enter the source code of the module to be built in the customer zone.

8. After the source code is edited, double-click check syntax in the process management area to check whether there is a syntax error.

9. Double-click synthesize-XST to complete integration.

10. Select simulation in view, right-click the project management area, select new source, select maid, and enter file name

11,

12,

13. Enter the test code. In this example, it is in the red line area of the customer zone. Other examples are not required!

14. Right-click the simulate behavioral model and select Properties to set simulation parameters.

15,

16. Right-click the project management area, select new source, and select implementation constraints File

17,

18. Enter the constraint code.

19. Double-click implement design to complete the implementation steps.

20. After implementation, view the pinout report through design summary. If the pin constraints are consistent with what you define, they are correct;

Otherwise, right-click synthesize-XST and implement design until the pin constraints are correct.

21. Double-click Generate programming file to generate a. Bit file.

22. Double-click Configure target device and click OK to download the. Bit file from impact.

23. Double-click Boundary Scan

24,

25. Click Initialize chain to check the existence of the Board.

26. Select the. Bit file to be downloaded.

27,

28,

29,

30. Place the cursor over the icon (the color will become deeper), right-click it, and select program. If the prompt "program successed" is displayed, it indicates

Downloaded successfully.

31. Observe whether the experiment results meet the design requirements.

 

Iii. Summary

1. The master's ise version is 13.3. Operations of different versions may be different.

2. Experiment code:

Led code:

module led(CLK,RST,LED,MODE);     input CLK;    input RST;    input [2:0] MODE;    output [7:0] LED;  reg [7:0] LED = 8'b10101010; reg [24:0] cnt_clk;  reg div_clk;  always @ (posedge CLK or posedge RST)beginif(RST)begincnt_clk <= 25'd0;div_clk <= 1'b0;endelse beginif(cnt_clk == 25'd9999999)begincnt_clk <=25'd0;div_clk <= ~div_clk;endelse begincnt_clk <= cnt_clk + 1'b1;div_clk <= div_clk;endendendalways @ (posedge div_clk or posedge RST)beginif(RST)beginLED <= 8'b10101010;endelse begincase (MODE)3'b000 :LED <= 8'b1;3'b001 :LED <= 8'b10;3'b010 :LED <= 8'b100;3'b011 : LED <= 8'b1000;3'b100 : LED <= 8'b10000;3'b101 :LED <= 8'b100000;3'b110 : LED <= 8'b1000000;3'b111 : LED <= 8'b10000000;endcaseendendendmodule

UCF constraint file:

NET "CLK" LOC = "C9" | IOSTANDARD = LVCMOS33;NET "CLK" PERIOD = 20ns HIGH 40%;NET "RST" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;NET "MODE<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP;NET "MODE<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP;NET "MODE<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP;NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;NET "LED<6>" LOC = "E9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;NET "LED<7>" LOC = "F9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;

Simulation code:

module led_test;// Inputsreg CLK;reg RST;reg [2:0] MODE;// Outputswire [7:0] LED;// Instantiate the Unit Under Test (UUT)led uut (.CLK(CLK), .RST(RST), .LED(LED), .MODE(MODE));always #5 CLK = ~CLK;initial begin// Initialize InputsCLK = 0;RST = 0;MODE = 0;// Wait 100 ns for global reset to finish#100;        // Add stimulus hereRST = 0;MODE = 3'b001;#10000;MODE = 3'b010;#10000;MODE = 3'b100;#1000 $stop;end      endmodule

3. I have learned the cc2430 board before. Now I start to learn FPGA, just a cainiao. But in general, hardware,

The chip information is very important. A circuit board is generally composed of a processor and several peripherals. Peripherals also have

It is connected, but it is all sitting on the circuit board. Chip data is required to obtain certain information for our use.

4. We hope that you will not be enlightened!