Step 6 of Self-writing CPU (2) Implementation of mobile operation commands

I will upload my new book "Write CPU by myself" (not published yet). Today is 21st, I try to write 6.2 mobile operation commands every thurs6.2.1 Implementation ideas. These six mobile operation commands can be divided into two categories: one is the commands that do not involve the special registers HI and LO, including movn and movz; the other involves the special register H.

I will upload my new book "Write CPU by myself" (not published yet). Today is 21st, I try to write 6.2 mobile operation commands every thurs6.2.1 Implementation ideas. These six mobile operation commands can be divided into two categories: one is the commands that do not involve the special registers HI and LO, including movn and movz; the other involves the special register H.

I will upload my new book "Write CPU by myself" (not published yet). Today is 21st articles. I try to write them every Thursday.

6.2 mobile operation instructions Implementation ideas 6.2.1 Implementation ideas

These six mobile operation commands can be divided into two types: one is the commands that do not involve the special registers HI and LO, including movn and movz, and the other is the commands that involve the special registers HI and LO, the options include mfhi, mflo, mthi, and mtlo. The first class is very easy to implement. The basic idea is similar to that in chapter 1 Implementation logic and shift operation commands. You only need to modify the ID and EX modules. The next class involves the special registers HI and LO. You need to add the HI and LO registers for OpenMIPS and the corresponding read/write control. The following describes the implementation methods respectively.

1. How to Implement the movn and movz commands

This is similar to the implementation of logic and shift operation commands in Chapter 1.

(1) In the decoding phase, the values of signals such as alusel_o, aluop_o, and wd_o of the destination Register address to be written are given, and the values of General registers whose addresses are rs and rt are read, however, here we need to add a step: Determine whether to write the destination register based on whether the value of the general register whose read address is rt is 0. Send the preceding results to the execution stage.

(2) the execution phase determines the final information of the destination register (including: whether to write, the destination Register address to write, and the written value) based on the incoming signal ), and pass the information to the access storage stage.

(3) the above information will be transmitted to the write-back stage. Finally, modify the destination register based on the information, or make no changes.

2. How to Implement the MTRs and mtlo commands

The two Commands need to write the HI and LO registers. Like the General registers previously implemented, the write operations on the HI and LO registers are carried out in the back-to-write phase.

(1) In the decoding stage, the value of alusel_o and aluop_o of the operator subtype is given based on the instruction, and the value of the general register whose address is rs is read. Because the common registers are not written to MTI and mtlo, wreg_o is WriteDisable and wd_o is 0.

(2) determine the status of the HI and LO registers to be written and the values to be written in the execution phase, and pass the information to the Access Memory phase.

(3) Transfer the information to the write-back stage.

(4) The value of the HI and LO registers is modified in the write-back phase based on the information.

3. How to Implement mfhi and mflo commands

The two Commands need to read the HI and LO registers and are designed to be read in the execution phase.

(1) In the decoding stage, the value of alusel_o and aluop_o of the subcomputation type is given based on the instruction. wreg_o is WriteEnable because of the destination register to be written, wd_o is the value of rd in the command, that is, the destination Register address.

(2) obtain the value of the HI or LO register in the execution phase as the data to be written into the destination register, and pass the information to the access storage phase.

(3) Transfer the information to the write-back stage.

(4) modify the destination register based on the information in the write-back phase.

Figure 6-2 shows the data flow after the Mobile Operation Command is added.

Comparison between Figure 6-2 and figure 5-7 shows the following differences.

• The HILO register module is added and put in the write-back phase.
• Transfer the values of HI and LO registers to the execution phase. A selection module is added in the execution phase to select the data to be involved in the operation. For mfhi and mflo commands, then the value of the HI and LO registers will be selected.

6.2.2 solutions to new data-related situations

Further consider the processing process of mfhi and mflo commands. These two Commands will read the values of HI and LO registers in the pipeline execution phase, if the values of HI and LO registers provided by the HILO module are used directly, the values of HI and LO registers may not be correct, at this time, the commands in the memory access and write-back phase may modify the HI and LO registers. The following program is used as an example.

1、    lui $1,0x0000          # $1 = 0x000000002、    lui $2,0xffff          # $1 = 0xffff00003、    mthi $0                # hi = 0x000000004、    mthi $1                # hi = 0x000000005、    mthi $2                # hi = 0xffff00006、    mfhi $4                # $4 = 0xffff0000

The HI register must be modified for commands 3, 4, and 5. When Command 6 is in the execution phase, command 5 is in the memory access phase, and command 4 is in the write-back phase, at this time, the value of the HI register is the 0x00000000 value just written to instruction 3. the HILO module transmits this value to the execution phase. If this value is used, an error will occur, which deviates from the concept of the program, the correct value should be the data to be written in command 5 of the current Memory Access stage, as shown in Figure 6-3.

Deja vu, isn't it? This is the data-related issue introduced in the previous chapter. The solution is to use data push. Feed the operation information of HI and LO registers of commands in the memory access and write-back stages to the execution stage, and determine the correct values of HI and LO registers based on the information in the execution stage.

To this end, you need to modify the data flow shown in Figure 6-4. Compared with figure 6-3, the main addition is to feedback the information in the access and write-back phases to the execution phases, input the selection module in the execution phase (as shown in the figure). If the mfhi and mflo commands are in the execution phase, the correct values of the HI and LO registers will be selected.

6.2.3 modification of System Structure

To implement the mobile operation commands, the OpenMIPS system structure must be supplemented and improved, as shown in Figure 6-5.

There are three main aspects.

(1) added the HILO module for implementing the HI and LO registers.

(2) In the execution phase, the EX module adds the whilo_o, hi_o, and lo_o interfaces to indicate whether to write HILO, the value of the HI register to be written, and the value of the LO register to be written. The modified information of HI and LO registers is transmitted to the write-back stage through the EX/MEM, MEM, and MEM/WB modules, and finally passed to the HILO module.

(3) The EX module in the execution stage adds input interfaces related to HI and LO registers, including the interfaces introduced to solve the data problems related to HI and LO registers, in section 6.3.3, we will provide a detailed introduction.

Next time, we will introduce the implementation of mobile operation commands and provide code. Stay tuned!