STM32 Clock Count

In STM32, there are five clock sources for HSI, HSE, LSI, LSE, PLL. In fact, four clock sources, as shown (gray-blue), PLL is a PLL clock that is multiplied by a phase-locked loop circuit. ①, HSI is a high-speed internal clock, RC oscillator, frequency of 8MHz.　　②, HSE is a high-speed external clock, can be connected to the quartz/ceramic resonator, or external clock source, frequency range of 4mhz~16mhz.　　③, LSI is a low-speed internal clock, RC oscillator, frequency of 40kHz.　　④, LSE is a low-speed external clock, the frequency of 32.768kHz quartz crystals. The ⑤, PLL is a phase-locked loop multiplier output, and its clock input source can be selected as HSI/2, HSE, or HSE/2. The multiplier can be selected as 2~16 times, but its output frequency must not exceed 72MHz.

 

The 40kHz LSI is used by independent watchdog IWDG, and it can also be selected as the clock source for real-time clock RTC. In addition, the clock source of the real-time clock RTC can also be selected LSE, or the 128 division of HSE.　　RTC's clock source is selected via rtcsel[1:0]. There is a full-speed USB module in the STM32, and its serial interface engine requires a clock source with a frequency of 48MHz.　　The clock source can only be obtained from the PLL output, optionally 1.5 or 1, that is, when a USB module is required, the PLL must be enabled, and the clock frequency is configured to 48MHz or 72MHz.　　In addition, the STM32 can choose a clock signal output to the MCO foot (PA8), you can choose to output the PLL 2, HSI, HSE, or system clock. The system clock SYSCLK, which is the clock source for most parts of the STM32. The system clock can be selected as a PLL output, HSI, or HSE. The system clock maximum frequency is 72MHz, it passes through the AHB divider to send to each module to use, the AHB divider may choose 1, 2, 4, 8, 16, 64, 128, 256, 512 divide.　　The clock for the AHB divider output is given to 5 modules using: ①, HCLK clock for AHB bus, kernel, memory, and DMA use.　　②, the system timer clock sent to cortex by 8.　　③, the idle run clock fclk that is sent directly to cortex. ④, give APB1 divider. APB1 Divider can choose 1, 2, 4, 8, 16 divided, its output for APB1 peripheral use (PCLK1, the maximum frequency 36MHz), the other way to the timer (timer) 2, 3, 4 times frequency multiplier used.　　The multiplier can choose 1 or twice times, the clock output for Timers 2, 3, 4 use. ⑤, give APB2 divider. APB2 crossover can choose 1, 2, 4, 8, 16, the output of the APB2 peripheral use (PCLK2, the maximum frequency 72MHz), and the other way to the timer (timer) 1 time multiplier used. The multiplier can choose 1 or twice times, the clock output for the timer 1 use. In addition, the APB2 divider has one output for the ADC divider, which is used for the ADC module.　　The ADC divider can be divided into 2, 4, 6, 8. In the above clock output, there are many with enable control, such as AHB bus clock, core clock, a variety of APB1 peripherals, APB2 peripherals and so on.　　When you need to use a module, be sure to first enable the corresponding clock.　　Note that the timer multiplier, when the division of the APB is 1 o'clock, its multiplier value is 1, otherwise its multiplier value is 2. Devices connected to the APB1 (low Speed peripherals) are: Power Interface, Backup interface, CAN, USB, i2c1, I2C2, UART2, UART3, SPI2, Windows watchdog, Timer2, Timer3, Timer4. Note that the USB module requires a separate 48MHz clock signal, but it should not be a clock for the USB module to work, but simply a clock to be used by the serial Interface Engine (SIE).　　The clock that the USB module works on should be provided by APB1. The devices connected to the APB2 (high-speed peripherals) are: UART1, SPI1, Timer1, ADC1, ADC2, all normal IO ports (PA~PE), and the second function IO port.   For microcontroller systems, the clock settings for the CPU and bus as well as the peripherals are very important, because there is no clock and no timing.   Since the clock is a thing from the inside out, the specific setting starts with the register.

The RCC register structure,Rcc_typedeff, is defined in the file "Stm32f10x.h" as follows: (v3.4 library) 1059 line->1081 line.

2. typedef struct
4. {
6. __io uint32_t CR;
8. __io uint32_t CFGR;
10. __io uint32_t CIR;
12. __io uint32_t apb2rstr;
14. __io uint32_t apb1rstr;
16. __io uint32_t Ahbenr;
18. __io uint32_t Apb2enr;
20. __io uint32_t Apb1enr;
22. __io uint32_t BDCR;
24. __io uint32_t CSR;
28. #ifdef STM32F10X_CL
30. __io uint32_t ahbrstr;
32. __io uint32_t CFGR2;
34. #endif/* STM32F10X_CL */
38. #if defined (STM32F10X_LD_VL) | | Defined (STM32F10X_MD_VL) | | Defined (STM32F10X_HD_VL)
40. uint32_t RESERVED0;
42. __io uint32_t CFGR2;
44. #endif/* STM32F10X_LD_VL | | STM32F10X_MD_VL | | STM32F10X_HD_VL * *
46. } rcc_typedef;

The general board only 8Mhz Crystal oscillator, and the enhanced maximum operating frequency of 72Mhz, obviously need to use PLL multiplier 9 times times, these settings need to be completed during the initialization phase. Using the HSE clock, the program sets the clock parameter flow:
1. Reset the RCC register to the default valueRcc_deinit;
2, open the external high-speed clock crystal HSERcc_hseconfig (rcc_hse_on);
3, waiting for external high-speed clock crystal workHsestartupstatus = Rcc_waitforhsestartup ();
4. Set AHB ClockRcc_hclkconfig;
5. Set the high-speed AHB clockRcc_pclk2config;
6, set the low speed AHB clockRcc_pclk1config;
7. Setting the PLLRcc_pllconfig;
8. Turn on the PLLRcc_pllcmd (ENABLE);
9. Wait for the PLL to workWhile (Rcc_getflagstatus (rcc_flag_pllrdy) = = RESET)
10. Set the system clockRcc_sysclkconfig;
11. Determine if the PLL is the system clockWhile (Rcc_getsysclksource ()! = 0x08)
12. Open the peripheral clock you want to usercc_apb2periphclockcmd ()/rcc_apb1periphclockcmd ( )To facilitate the explanation, use the RCC Setup function of the routine and explain it in the form of Chinese annotations:

2. static void Rcc_config (void)
4. {
8. /* Here is a reset of the RCC settings, similar to the register reset */
10. Rcc_deinit ();
14. /* Enable external high-speed crystal */
16. Rcc_hseconfig (rcc_hse_on);
20. /* Wait for high-speed crystal stability */
22. Hsestartupstatus = Rcc_waitforhsestartup ();
26. if (Hsestartupstatus = = SUCCESS)
28. {
30. /* Enable flash pre-read buffer */
32. Flash_prefetchbuffercmd (flash_prefetchbuffer_enable);
36. /* Flash is waiting, 2 is for the high-frequency clock, these two sentences are not directly related to RCC, you can temporarily skip */
38. Flash_setlatency (flash_latency_2);
42. /* HCLK = SYSCLK set high speed bus Clock = system clock */
44. Rcc_hclkconfig (RCC_SYSCLK_DIV1);
48. /* PCLK2 = HCLK set slow bus 2: = high speed bus clock */
50. Rcc_pclk2config (RCC_HCLK_DIV1);
54. /* PCLK1 = HCLK/2 Set the clock for low speed bus 1 = two-way clock
56. Rcc_pclk1config (RCC_HCLK_DIV2);
60. /* ADCCLK = PCLK2/6 Set ADC Peripheral clock = Six frequency of low-speed bus 2: */
62. Rcc_adcclkconfig (RCC_PCLK2_DIV6);
66. /* Set PLL clock output to 72MHz using HSE (8MHz) as entry clock */
68. That's a very important sentence.
70. /* Use phase-locked loop to speak external 8Mhz Crystal 9 times Octave to 72Mhz */
72. Rcc_pllconfig (Rcc_pllsource_hse_div1, rcc_pllmul_9);
76. /* Enable PLL enabling phase-locked loop */
78. Rcc_pllcmd (ENABLE);
84. /* Wait till PLL is ready for phase-locked loop output Stable */
86. while (Rcc_getflagstatus (rcc_flag_pllrdy) = = RESET)
88. {}
92. /* Select PLL as System clock source sets the phase-locked loop output to the systems clock */
94. Rcc_sysclkconfig (RCC_SYSCLKSOURCE_PLLCLK);
98. /* Wait till PLL is used as system clock source waits for verification success */
100. while (Rcc_getsysclksource ()! = 0x08)
102. {}
104. }
108. /* Enable FSMC, Gpiod, Gpioe, Gpiof, Gpiog and AFIO clocks */
110. Enable peripheral interface bus clock, pay attention to the subordinate situation of each peripheral, different chip distribution, then check the manual can
112. Rcc_ahbperiphclockcmd (RCC_AHBPERIPH_FSMC, ENABLE);
116. Rcc_apb2periphclockcmd (Rcc_apb2periph_gpiod | Rcc_apb2periph_gpioe |
118. Rcc_apb2periph_gpiof | Rcc_apb2periph_gpiog |
120. Rcc_apb2periph_afio, ENABLE);
122. }

The above procedure can be seen that the system clock setting is more complex, the more peripherals, need to consider the more factors. At the same time this setting is also a regular, set parameters are also ordered specification, which should be noted in the application, for example, the PLL settings need to be enabled, once the PLL enables the parameters can not be changed. After this set, because my board is 8Mhz crystal oscillator, so the system clock is 72Mhz, high-speed bus and low Speed Bus 2 are 72Mhz, low-speed bus 1 for the 36MHZ,ADC clock for the 12MHZ,USB clock after 1.5-way set to achieve 48Mhz data transmission. The general clock setting needs to consider the source of the system clock, whether it is an internal RC or an external crystal or an external oscillator, if the PLL is required. Then consider the internal bus and the external bus, and finally consider the peripheral clock signal. To comply with the first octave as the CPU clock, and then in by the outside division, the subordinate to the superior principle is somewhat similar to the standardization of PCB mapping requirements, here also note:

InSTM32, connected to theAPB1 (Low Speed Peripherals)The devices on the device are: Power Interface, Backup interface,CAN,USB,i2c1,I2C2,UART2,UART3,SPI2, window watchdog,Timer2,Timer3,Timer4.

connected in APB2 ( high-speed peripherals are: gpio_a-e usart1 , ADC1 adc2 Span style= "font-family: the song Body;" >, ADC3 , TIM1 tim8 Span style= "font-family: the song Body;" >, spi1 , all

Examples of programs:

APB1 ( Low Speed Peripherals )

Rcc_apb1periphclockcmd (Rcc_apb1periph_can, ENABLE);

APB2(High speed peripherals)

Rcc_apb2periphclockcmd (Rcc_apb2periph_gpioa, ENABLE);

Rcc_apb2periphclockcmd (Rcc_apb2periph_usart1 | Rcc_apb2periph_gpioa, ENABLE);

Transferred from: http://blog.chinaunix.net/uid-21658993-id-3129667.html

STM32 Clock Count