STM32 Learning Note 8 (DMA Controller)

DMA Introduction (1)

DMA, called Direct Memory access, which is used to provide high-speed data transfer between peripherals and memory or between memory and memory. When the CPU initializes this transfer action, the transfer action itself is implemented and completed by the DMA controller. DMA transmission is important for efficient embedded system algorithms and networks. DMA transmission mode without the direct control of the CPU transmission, and no interruption of processing to retain the site and the recovery site process, through the hardware for RAM and I/O equipment to open a direct data transmission path, can make the CPU efficiency greatly improved. The STM32 has a maximum of 2 DMA controllers (DMA2 only in large-capacity products), DMA1 has 7 channels, and DMA2 has 5 channels. Each channel is designed to manage requests from one or more peripherals for memory access. There is also an arbitrator to coordinate the priority of each DMA request.

DMA requests from peripherals (TIMX, ADCs, SPIx, I2CX, and USARTX) are either logically or input to the DMA controller, which means that only one request can be valid at the same time. The DMA request of the peripheral can be turned on or off independently by setting the control bit in the corresponding peripheral register.
Table 1 is a list of the DMA1 channels:

Table 1 DMA each channel list

Logical OR, several DMA1 requests for Channel 1 (ADC1, Tim2_ch3, Tim4_ch1), which are either through logic or to channel 1, so that we can only use one of them at the same time. The other channels are similar.

DMA Registers

Note: In all registers listed below, all bits related to channel 6 and Channel 7 do not apply to DMA2 because DMA2 has only 5 channels.

DMA Interrupt Status Register (DMA_ISR)

If these interrupts are turned on in Dma_isr, they will jump to the interrupt service function after the condition is reached, and if not, we can also get the status of the current DMA transfer by querying these bits. What is commonly used here is the TCIFX, the sign that the channel DMA transfer is complete or not. Note that this register is read-only, so after the bits have been set, they can only be cleared by other operations.

The DMA interrupt flag clears the register (DMA_IFCR).

DMA Introduction (2):The stm32f10x is configured with two separate DMA controllers, each connected to a different peripheral. The DMA1 has 7 channels, the DMA2 has 5 channels, and although the channels are independent, DMA can only process requests for one channel. DMA is characterized by the direct use of the data bus when disconnected from the CPU, the data transmission in the peripheral and memory self-test. Frees up CPU consumption during data transfer. DMA works similar to interrupt response, and when the DMA time of the peripheral is generated, a DMA request is generated, and the DMA controller chooses the corresponding DMA channel request to perform the data transfer. 1. The priority configuration is divided into software and hardware two-piece configuration: Software configuration has 4, set in DMA_CCRX, 00: Low 01:10: High 11: Highest, visible software set priority than the actual number of DMA channels, Therefore, the decision of the hardware priority is the same as the two channel software priority, the comparison channel number, the lower sequence number has a higher priority. 2. Data transfer settings Once the DMA responds to a peripheral request, it is necessary to start transferring data between peripherals, which is to provide the address of the source and destination addresses in the Dma_cparx register to set the peripheral register, and the address of the data memory in the Dma_cmarx register. The direction of the transmission is then set in Dir of the Dma_cmarx register. The psize and msize bits in the DMA_CCRX register do not set the peripheral and memory bit width, generally to maintain a two bit width consistent. If the inconsistency is also mentioned in the manual, the half-word write does not go wrong. 3. Transmission mode typically a single request will transmit a sequence of data sequentially, which is transmitted by setting the Dma_cndtrx setting, and the data will be decremented by 1 if not transmitted. Set the Pinc and MINC flag bit settings in the DMA_CCRX register to turn on the incremental mode, the conditional descent that turns on the increment will increase or decrease the address according to the bit width. Loop: The CIRC setting in the DMA_CCRX register turns cycle mode on, and if on, automatically resets the count value and address after a request is transferred, and starts the transfer again. 4. The transmission between the memory is enabled by setting the MEM2MEM bit in the DMA_CCRX register, and when the software sets the en bit in the DMA_CCRX register to start the DMA channel, the DMA transfer will start immediately. DMA channel hardware request is assigned to external peripherals, and the software is used to start the communication between the memory. The 5.DMA CPU interrupt request has three interrupt types, all connected to one interrupt channel. This interrupt can be configured to enter the interrupt service function after the data transfer is completed, data processing, such as ad sampling and transmission to the memory, the software filtering, mean, of course, can also be used to query the way.   According to the above, when using DMA read Rule Group continuous conversion of the ad value,The basic steps are as follows: A. Enable AD1 DMA request, B. Set the DMA bit continuous loop (as needed) and enable the DMA1 channel 1.c where the AD1 is located. The peripheral address is set to the AD1 address, and the storage address is based on the program set to AD sample worth array. D. Set the bit width to half word, set priority, set CNDTR to 1, transfer one data at a time, data length is half word. E. Enable DMA1 so that when the ADC1 completes one by one data per conversion, the DMA channel is generated, the data is transferred to the specified memory, and it is noted that it is reasonable to arrange the sampling and storage in a manner that conforms to the sequence requirements of the array. The specific process should be used in accordance with the actual needs.   [CPP]View Plaincopyprint?

2. void Init_dma ()
4. {
6. Dma_inittypedef dma_initstructure;
8. Dma_deinit (DMA1_CHANNEL1);
10. Dma_initstructure.dma_peripheralbaseaddr = (uint32_t) &ADC1->DR;
12. Dma_initstructure.dma_memorybaseaddr = (uint32_t) &ADCConvertedValue;
14. Dma_initstructure.dma_dir = DMA_DIR_PERIPHERALSRC; //  
16. Dma_initstructure.dma_buffersize = 1; //  
18. Dma_initstructure.dma_peripheralinc = dma_peripheralinc_disable; //  
20. Dma_initstructure.dma_memoryinc = dma_memoryinc_disable; //  
22. Dma_initstructure.dma_peripheraldatasize = Dma_peripheraldatasize_halfword; //  
24. Dma_initstructure.dma_memorydatasize = Dma_memorydatasize_halfword; //  
26. Dma_initstructure.dma_mode = Dma_mode_circular;
28. dma_initstructure.dma_priority = Dma_priority_high;
30. dma_initstructure.dma_m2m = dma_m2m_disable;
32. Dma_init (Dma1_channel1, &dma_initstructure);
34. / * Enable DMA1 channel1 * /
36. Dma_cmd (Dma1_channel1, ENABLE);
38. }

The actual DMA idea is very simple, the Peripheral DMA event request Enable, DMA enable the corresponding channel, set the source address destination address, can be transmitted.

STM32 Learning Note 8 (DMA Controller)