Stm32 Register Edition Learning note 06 Input capture (ETR pulse count)

STM32 external pulse ETR pin:tim1-->pa12; timer2-->pa0;timer3-->pd2; TIMER4-->PE0 ...

1.TIM2 PA0 Count Configuration steps

① turn on TIM2 clock, configure PA0 input

APB1 Peripheral Reset Register (RCC_APB1RSTR)

APB2 Peripheral Clock Enable register (RCC_APB2ENR)

Set 1 to open. Clear 0 closed.

eg:rcc->apb1enr|=1<<0; Enable TIM2 clock

rcc->apb2enr|=1<<2; //enable Porta clock

Configuring I/O ports: See Stm32 Register Edition Learning Note the configuration of the Gpio port.

eg:gpioa->crl&=0xfffffff0; PA0 before clearing the settings
GPIOA->CRL|=0X00000008;//PA0 input
GPIOA->ODR|=0<<0;//PA0 drop down

② set arr and PSC for TIM2

Automatic reload Register (Timx_arr)

Prescaler (TIMX_PSC)

③ Setting the CCMR1 of TIM2

The TIM2_CCMR1 register controls the mode of input capture 1 and 2, including mapping relationships, filtering, and dividing. This requires that Channel 1 be set to input mode, and the IC1 is mapped to TI1 (Channel 1) and does not use a filter (increase response speed).

Capture/Compare Mode Register 1 (TIMX_CCMR1)

Input Capture Mode:

Eg: tim2->ccmr1|=1<<0; CC1S=01 Select input IC1 map to TI1

tim2->ccmr1|=1<<4; IC1F=0001 configuration input filter to Fck_int sampling, valid after 2 events
tim2->ccmr1|=0<<10; IC2PS=00 configuration input divider, no crossover

④ set TIM2 ccer, turn on input capture, and set rising edge capture

The Tim2_ccer register is the switch of the timer, and the edge of the input capture can be set.

Capture/Compare enable register (timx_ccer)

Eg: tim2->ccer|=0<<1;//cc1p=0 rising edge capture

tim2->ccer|=1<<0; Cc1e=1 allows capturing the value of the counter to the capture register

⑤ set TIM2 dier to enable capture and update interrupts, and write interrupt service functions

dma/Interrupt enable register (Timx_dier)

Eg:tim2->dier|=1<<1;//Allow capture interrupt

tim2->dier|=1<<0; Allow update interrupts

⑥ Setting the TIM2 CR1 enable timer

Finally turn on the timer counter switch, start the TIM2 counter, start the input capture.

Control register 1 (TIMX_CR1)

2.TIM2 PA0 Counting Application

1 //Timer 2 Channel 1 input capture configuration2 //arr: Auto Reload values3 //PSC: Clock Prescaler frequency4 voidTim2_cap_init (U16 arr,u16 PSC)5 {         6rcc->apb1enr|=1<<0;//TIM2 Clock Enable7rcc->apb2enr|=1<<2;//Enable Porta clock8      9gpioa->crl&=0xfffffff0;//PA0 before clearing the settingsTengpioa->crl|=0X00000008;//PA0 Input Onegpioa->odr|=0<<0;//PA0 drop down A        -tim2->arr=arr;//Set counter Auto reload value -tim2->psc=psc;//Prescaler the  -tim2->ccmr1|=1<<0;//cc1s=01 Select input IC1 map to TI1 -tim2->ccmr1|=1<<4;//ic1f=0001 Configuration Input filter to Fck_int sampling, valid after 2 events -tim2->ccmr1|=0<<Ten;//ic2ps=00 Configuration input divider, no crossover +  -tim2->ccer|=0<<1;//cc1p=0 Rising edge capture +tim2->ccer|=1<<0;//cc1e=1 allows capturing the value of the counter to the capture register A  attim2->dier|=1<<1;//allow capture interrupts -tim2->dier|=1<<0;//Allow update interrupts -tim2->cr1|=0x01;//Enable timer 2 -My_nvic_init (2,0, TIM2_IRQN,2);//preemption 2, sub-priority 0, group 2 - } -  in //Timer 2 Interrupt Service Program - voidTim2_irqhandler (void) to {              + U16 TSR; -Tsr=tim2->SR; the         if(tsr&0x02)//Capture 1 Occurrence capture event *         {     $cishu++;Panax Notoginseng              -         }                                                 theTim2->sr=0;//clear Interrupt Flag bit +}

// test. C Tim2_cap_init (0);          while (1) {    printf ("cishu:%d us\r\n", Cishu);             }

I do not know why CNT reading is 0 ...

Stm32 Register Edition Learning note 06 Input capture (ETR pulse count)