Storage space allocation and Startup Mode of linux-2.6.27 porting to at91sam9260 platform terminal (01) _ 9260

From: http://blog.csdn.net/reille/article/details/5632648

As the platform for the company's terminal products is changed from Samsung's 2440 to 9260 (probably because 9260 is more suitable for industrial scenarios), considering that subsequent projects may also adopt this platform to keep pace with the times, therefore, we can use our free time to learn this platform!

 

According to the Convention, first understand the storage space allocation of 9260 and its startup method:

1. 9260 of the bus is 32bit, so the storage space is 4 GB, divided into 16 banks, each of which is 256 MB, where bank0 is mapped to internal memory, that is, the start memory, the internal ROM and the internal two SRAM, the start memory is different because of the selected Start mode; bank1-bank8 ing for external memory, respectively corresponding to the chip selected 0 to the chip selected 7.

 

2. Like 2440, 9260 is always started from address 0x0. Therefore, you need to focus on who is mapped to address 0. The ing is determined by two parameters. One hardware parameter is the BMS pin level state, and the other software setting parameter is the remap parameter. Remap is 0: When the BMS pin is detected to be 1, the internal ROM is mapped to address 0x0. When the BMS pin is detected to be 0, as mentioned above, the image 0 is mapped to the address 0x0. Therefore, two startup modes are implemented through the level settings of the BMS pin.

 

3. Check that the BMS pin is 0: bank1 indicates that the corresponding chip 0 is Ebi (External Bus Interface), and external memory is connected. Generally, it is started from norflash or nandflash. From the data manual, we can see that 3 pieces have been reserved for nandflash in the 9260 processor. Therefore, if you connect norflash to 0, you can enable norflash.

4. When the BMS pin is 1, the internal ROM is mapped to the address 0x0. When the internal ROM of 9260 is mapped to address 0x0, the program first scans two SPI dataflash files to check whether there are eight exception vectors, that is, the content of the first 28bytes is detected. If it is an exception vector, it indicates that the system can be guided. At this time, according to the size of vector 6, determine the size to be loaded to the SRAM, and then remap (remap), so that the SRAM becomes the address 0, then the program jumps to the 0 address for execution; if two SPI
If dataflash does not have a corresponding vector, it is switched to NAND Flash detection. If eight abnormal vectors are detected, it indicates that NAND flash can be guided by the same method as above.

 

6. Conclusion:

When we need to start from nor flash, the BMS pin is set to a low level, so that the memory bank1 in which nor flash is located, that is, the EBI chip is selected 0 and mapped to address 0, in this case, it starts from nor flash. When we need to start from NAND Flash, the BMS pin is set to a high level, and the internal ROM is mapped to address 0, the Program (bootloader inside the chip) in Rom has detected two SPI
After dataflash, when detecting that NAND Flash has a corresponding vector, the code of vector 6 marked in NAND Flash will be automatically copied to the SRAM, and then re-mapped, that is, the internal SRAM is mapped to the address 0x0 and the address 0x0. The system is executed.

When we start from nor flash, There is nothing special to say. At this time, we ignore the content of bank0, namely the content in the SRAM and Rom, and we can use a larger amount of SDRAM to do things. When we start from NAND Flash, a small part of the NAND Flash startup code is copied to the SRAM (at this time, the Rom is mapped to 0, and the SRAM is after it), and then REMAP, the SRAM is mapped to the address 0, and the CPU automatically jumps to the address 0, that is, the execution of a small part of the startup Code. At this time, the startup code can also be executed with a larger amount of SDRAM ~

 

When NAND Flash is started, the bootloader inside the chip (in the internal ROM) will throw Bootstrap to the SRAM to run, and then Bootstrap will initialize the SDRAM and NAND/dataflash, load the uboot or user program from the NAND or dataflash to the SDRAM for running.

 

The company's terminal products use nand flash Boot. From the schematic diagram, the BMS pin is set to a high level, as we have analyzed!