Structure of instruction Cache in OR1200

The following excerpt from the "Step-by-step core-Soft core processor internal design analysis," a book

12.3 Icache Structure

The files implemented in OR1200 are OR1200_IC_TOP.V, OR1200_IC_FSM.V, OR1200_IC_TAG.V, OR1200_IC_RAM.V, or1200_ and Icache. SPRAM.V, Icache module, IC_FSM module, Ic_tag module, Ic_ram module, and one-port RAM are implemented respectively. The IC_FSM, Ic_tag, ic_ram modules are instantiated in Icache. The Ic_tag, Ic_ram module is instantiated with the port RAM. 12.4 of what you see. The Ic_tag, Ic_ram can be called the data part, IC_FSM can be called the control section, the data part of the search operation, the results of the search (Icache hit or lost target) to the control section, the control section based on the results of the next operation, for example: when the loss of target. The control section reads in 16 bytes to fill the Icache.

This section describes the data section and the control section in Icache.

12.3.1ICache module connection to the remaining modules

Before the introduction of the Icache Data section, the control section. First, the connection between the Icache module and the remaining modules is given. facilitates the subsequent analysis.

In the 3rd chapter, the connection between Icache and Qmem and Wb_biu is given when Qmem is introduced. It is known from Icache and both that both are wishbone bus interfaces.

Icache's full interface 12.5 is seen.

The following points are explained:

(1) Icache in addition to having a wishbone bus interface, but also has a special Register access interface: Spr_cs, Spr_write, spr_dat_i. This indicates that there are special registers in the Icache. However, this special register is not readable (no Spr_dat_o interface) and can only be written (with Spr_dat_i interface).

(2) The output of the QMEM has an interface icqmem_ci_o, the signal is actually directly from the IMMU, recalling that each table item in ITLB has a sign-bit CI. Indicates whether the corresponding page can be cached, and the value is finally output to Icache through Qmem's icqmem_ci_o. Suppose you want to read the contents of a memory block, but the value of Icqmem_ci_o is 1. Then the memory block is not possible in icache, no need to find Icache. Read directly from memory and, conversely, assume that the value of Icqmem_ci_o is 0, and first find it in Icache.

(3) The interface name between Icache and Wb_biu is in the form of icbiu_xxx_x, and the interface name between Icache and Qmem is in the form of icqmem_xxx_x, so the location of the interface can be known by name.

12.3.2 Data section of Icache

The data portion of the Icache contains Ic_tag, Ic_ram, and its main body is a one-port RAM.

The two together make up the folder table in Figure 12.2. Find what you see in method 12.6.

The default Icache settings are used here or OR1200.

Ic_tag co-owns 512 table entries, each of which includes the identity, V, which identifies the high 19 bits of the physical address. The Ic_ram includes data for Icache. The data here is the instruction. Ic_ram 4 table entries (each table entry is a word, with 4 bytes) and one of the table entries in Ic_tag is a line in the Icache folder table. For example, the 1th table entry in Ic_tag and Ic_ram in address 4-7 make up the line1 of the Icache folder table. When you want to refer to the Ic_tag, you need to read the command address 4-12 bits of the value as an index to find Ic_tag, get ic_tag the corresponding table entry, the table entry is returned to the Icache module, the latter to infer whether the cache is hit. At the same time looking for the Ic_tag table, using the value of the physical address 2-12 bits as the index to read out the corresponding words in Ic_ram, assuming Icache hit, then the words read from Ic_ram are required instructions.

The Ic_tag is implemented via a one-port RAM with the main code such as the following:

Or1200_ic_tag.vmodule Or1200_ic_tag (                             //ic_tagclk, rst, addr, en, we, datain, tag_v, tag);//Data width DW is 20, including address 19 bits high, Valid flag bit vparameter DW = ' or1200_ictag_w;            The address width is 9                parameter aw = ' Or1200_ictag;   ... Or1200_spram #                 //Instantiate A-port Ram     (   . AW (' Or1200_ictag),  . DW (' or1200_ictag_w)      )   ic_tag0             // The data that is read from the DOQ contains the identity, the valid bit     (   . CLK), the. CE (en),.   we,.   addr (addr),           . Di (DataIn),  . DOQ ({tag, tag_v}));   Endmodule

Ic_ram is also implemented via a port RAM, with the main code such as the following:

Or1200_ic_ram.vmodule Or1200_ic_ram (                                 //ic_ramclk, rst, addr, en, we, DataIn, dataout);p arameter dw = ' Or1200_operand _width;                 Data width is 32bitparameter aw = ' or1200_icindx;                        Address width is   one ... Or1200_spram #                                     //Instantiate A-port Ram     (  . AW (' Or1200_icindx),. DW ()      )   ic_ram0     (  . CLK),     . CE (en),   . We (We[0]),.    addr (addr),.            di (datain),   . DOQ (Dataout));   Endmodule

12.3.3 Icache in the control section

The control part of the Icache control Icache the next operation according to the results of Ic_tag and Ic_ram, and the Icache control part is mainly implemented in the IC_FSM module. The body of the IC_FSM module is a state machine with three states: Idle, Cfetch, LREFILL3. Definitions such as the following:

OR1200_DEFINES.V ' define Or1200_icfsm_idle2 ' d0 ' define OR1200_ICFSM_CFETCH2 ' D1 ' define OR1200_ICFSM_LREFILL32 ' d2// This state, although defined, is not used, so the IC_FSM state machine has only 3 states ' define OR1200_ICFSM_IFETCH2 ' D3       

The state transitions are seen in 12.7.

When the processor is reset, it is idle and enters the Cfetch state when the reference is to be taken. In this case there are three cases:

• Suppose Icache hit. The instructions found from Ic_ram are then returned to the processor. Keep Cfetch state at the same time
• Suppose the icache loses its target. The required instruction is read from memory and then enters the LREFILL3 state. In this state, the 3 words remaining in the memory block of the required instruction are read out, that is, the 4 words of the memory block in which the required instruction resides are read into the Icache, and then back to the idle state
• Assume that the memory block in which the required instruction is located prohibits caching (that is, CI is 1). Then the required instruction is read from memory. And then back to the idle state

The above three cases are also icache three use scenarios, this chapter will be combined with code in-depth analysis of these three scenarios icache work process. Includes state transitions in the IC_FSM state machine, when readers will have a deeper understanding of their friends.

12.3.4 Icache Data part and control part of external interface

IC_FSM, Ic_tag, Ic_ram are all instantiated in Icache. The example statements are as follows:

OR1200_IC_TOP.V......OR1200_IC_FSM OR1200_IC_FSM (                      //Case IC_FSM.CLK (CLK),.   rst (RST),. Ic_en (Ic_en),. icqmem_ Cycstb_i (Icqmem_cycstb_i),. Icqmem_ci_i (Icqmem_ci_i),. Tagcomp_miss (Tagcomp_miss),. Biudata_valid (Icbiu_ack_i),. Biudata_error (Icbiu_err_i),. START_ADDR (Icqmem_adr_i),. SAVED_ADDR (SAVED_ADDR),. Icram_we (Icram_we),. Biu_read ( Icfsm_biu_read),. First_hit_ack (Icfsm_first_hit_ack),. First_miss_ack (Icfsm_first_miss_ack),. First_miss_err ( Icfsm_first_miss_err),. Burst (Icfsm_burst),. Tag_we (Icfsm_tag_we)); Or1200_ic_ram Or1200_ic_ram (                      //Case Ic_ RAM.CLK (CLK),. RST (RST),. Addr (ic_addr[' or1200_icindxh:2]),. En (Ic_en),. We (Icram_we),. DataIn (To_icram),. Dataout ( From_icram)); Or1200_ic_tag Or1200_ic_tag (                      //Case IC_TAG.CLK (CLK),. RST (RST),. Addr (Ictag_addr),. En (Ictag_en),. We (Ictag_we),. DataIn ({ic_addr[31: ' Or1200_ictagl], ictag_v}),. Tag_v (Tag_v),. Tag (tag));

Refer to the above example of the statement obtained in Figure 12.8. The interface of IC_FSM, Ic_tag and Ic_ram modules is given. As well as the corresponding variables of each interface connected to Icache, the left side of each module is the input interface, the right is the output interface, each module is the interface name, and the name on the external pin represents the corresponding variable in the Icache.

Figure 12.8, Ic_tag output Tag_v, tag is a lookup result, icache based on this finding results set the value of the signal Tagcomp_miss, the signal indicates whether the Icache hit, and the signal input to the IC_FSM of the same name interface, IC_ The FSM makes state transitions and outputs control signals based on this value. To do the next step.

It is often necessary to refer to this figure when analyzing Icache later in this chapter. Readers do not need to clarify the meaning of the interface at this time, the author left in the use of the interface when the introduction.

Structure of instruction Cache in OR1200