Summary of assembly instructions

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Introduction to Computer Register classification
General instructions for computer registers
I. Common directives
Second, arithmetic operation instruction
Three, the logic operation instruction
Iv. sequence of instructions
V. Program JUMP Instruction
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Introduction to Computer Register classification:
The registers included with the 32-bit CPU are:
4 Data registers (EAX, EBX, ECX, and edx)
2 variable address and pointer registers (ESI and EDI) 2 pointer registers (ESP and EBP)
6 segment Registers (ES, CS, SS, DS, FS and GS)
1 instruction Pointer Register (EIP) 1 flag Register (EFLAGS)
1. Data register
Data registers are primarily used to store information such as operands and results of operations, thus saving the time required to consume the bus and access memory for the number of read operations.
The 32-bit CPU has 4 general-purpose registers of 32-bit eax, EBX, ECX, and edx.
Access to low 16-bit data does not affect data that is 16 bits high.
These low 16-bit registers are named: AX, BX, CX, and DX, which match the registers in the previous CPU.
The 4 16-bit registers can be divided into 8 independent 8-bit registers (Ax:ah-al, BX:BH-BL, CX:CH-CL, DX:DH-DL), each with its own name and can be accessed independently of each other.
Programmers can use this "can-be-fit" feature of data registers to handle word/byte information flexibly.
Register eax are often called accumulators (accumulator), and operations with accumulators may take less time. can be used for multiplication, divide, input/output and other operations, the use of high frequency;
The register EBX is called the base register. It can be used as a memory pointer;
The register ECX is called the Count register.
In the loop and string operation, it is used to control the number of cycles; In a bitwise operation, when moving multiple bits, CL is used to indicate the number of bits to be shifted;
The register edx is called the data register. It can participate in the operation as the default operand or the port address of the I/O when the multiply, divide operation is performed.
In 16-bit CPUs, AX, BX, CX, and DX cannot hold the address of a storage unit as a base address and a variable-address register.
In a 32-bit CPU, its 32-bit registers eax, EBX, ECX, and edx can not only transmit data, but also hold the results of the arithmetic logical operation of the staged data.
They are also available as pointer registers, so these 32-bit registers are more versatile.
2. Variable address register
The 32-bit CPU has 2 32-bit general-purpose registers ESI and EDI.
Its low 16 bits correspond to Si and di in the previous CPU, and access to low 16 bits of data does not affect high 16 bits of data.
Registers esi, EDI, Si, and di are referred to as the variable-address registers (Index register), which are mainly used to hold the offset of the storage unit within the segment,
They can be used to address a variety of memory operations, providing convenient access to storage units in different addresses.
The variable address register is not divisible into 8-bit registers. As a general register, the operands and results of arithmetic logic operations can also be stored.
They can be used as a general memory pointer. During the execution of the string manipulation instructions, they have specific requirements, and they also have special functions.
3. Pointer register
Its low 16 bits correspond to the BP and SP in the previous CPU, and access to low 16-bit data does not affect the high 16-bit data.
The 32-bit CPU has 2 32-bit general-purpose registers EBP and esp.
They are primarily used to access storage units within the stack and provide for:
EBP is the base pointer (base Pointer) register, which allows direct access to data in the stack;
The ESP is a stack pointer (Pointer) register, which is used to access only the top of the stack.
Register EBP, ESP, BP, and SP, called the Pointer Register (Pointer register), are primarily used to store the offset of the storage unit within the stack,
They can be used to address a variety of memory operations, providing convenient access to storage units in different addresses.
The pointer register is not divisible into 8-bit registers. As a general register, the operands and results of arithmetic logic operations can also be stored.
4, Segment Register
Segment registers are set according to the management mode of memory fragmentation. The physical address of the memory unit is combined with the value of the segment register and an offset
So that the two less digits can be combined into a memory address that accesses the larger physical space.
Segment registers inside the CPU:
ecs--Code Segment Register, whose value is the segment value of the code snippet;
eds--Data Segment Register, whose value is the segment value of the data segment;
ees--Additional segment Register (Extra Segment register), whose value is the segment value of the additional data segment;
The ess--stack segment register (stack Segment register), whose value is the segment value of the stack segment;
efs--Additional segment Register (Extra Segment register), whose value is the segment value of the additional data segment;
The egs--additional segment register (Extra Segment register), whose value is the segment value of the additional data segment.
In a 16-bit CPU system, it has only 4 segment registers, so the program can be accessed directly at most 4 of the segments being used at any given time, and in 32-bit
In a microcomputer system, it has 6 segment registers, so the program developed in this environment can access up to 6 segments at the same time.
32-bit CPUs have two different ways of working: real-mode and protection. In each of these ways, the function of the segment register is different. The relevant provisions Jane
The single description is as follows:
Real mode: The first 4 segment registers CS, DS, ES, and SS have exactly the same meaning as the corresponding segment registers in the previous CPU, the logic of the memory unit
The address is still in the form of "segment value: Offset". To access data within a memory segment, the offset of the segment register and the storage unit must be used.
Protection mode: In this way, the situation is much more complicated, the loading segment register is no longer a segment value, but a value called "Selector".
5. Instruction Pointer Register
The 32-bit CPU expands the instruction pointer to 32 bits, and the lower 16 bits of the EIP,EIP are the same as the IP in the previous CPU.
The instruction Pointer Eip, IP (instruction Pointer) is the offset of the code snippet that holds the next instruction to be executed.
In a system with prefetch instruction functionality, the next instruction to be executed is usually pre-provisioned to the instruction queue, unless a transfer situation occurs.
Therefore, when you understand their functionality, there is no case of instruction queuing.
6. Flag Register
First, the result of the operation of the flag
1. Carry Mark CF (Carry flag)
The carry flag CF is mainly used to reflect whether the operation produces rounding or borrow. If the highest bit of the result of the operation produces a carry or borrow, its value is 1, otherwise its value is 0.
The use of this flag bit is: the addition and subtraction of the number of characters (bytes), the size of the unsigned number comparison operation, the shift operation, the word (byte) between the shift, specifically change the CF value of the instructions.
2, Parity Mark PF (Parity flag)
The parity Mark PF is used to reflect the parity of the number of "1" in the result of the operation. If the number of "1" is even, the value of PF is 1, otherwise its value is 0.
The PF can be used for parity checking, or for generating parity bits. In the process of data transfer, in order to provide the reliability of the transmission, if the use of parity method, you can use the flag bit
.
3. Auxiliary carry sign AF (auxiliary Carry flag)
The value of the secondary carry Flag AF is set to 1 if the following occurs, otherwise its value is 0:
(1), in the word operation, the occurrence of low-byte high-byte rounding or borrow;
(2), when the byte operation, occurs when the low 4-bit to high 4-bit carry or borrow.
For the above 6 operation result flag bits, in the general programming case, the use frequency of the flag bit CF, ZF, SF and of is higher, while the use frequency of the flag bit PF and AF is low.
4, 0 Mark ZF (Zero flag)
The 0 symbol ZF is used to reflect whether the result of the operation is 0. If the result of the operation is 0, its value is 1, otherwise its value is 0. This flag bit can be used when judging whether the result of the operation is 0 o'clock.
5. Symbol SF (sign flag)
The symbolic symbol SF is used to reflect the symbolic bit of the result of the operation, which is the same as the highest bit of the result. In the microcomputer system, the symbolic number is represented by the code, so the SF also reflects the results of the operation.
plus sign. When the result of the operation is positive, the SF value is 0, otherwise its value is 1.
6. Overflow mark of (Overflow flag)
The overflow flag of is used to reflect whether the signed number plus minus operation results in overflow. If the result of the operation exceeds the range that can be represented by the current number of operations, it is called overflow, and the value of of is set to 1, no
Then, the value of is cleared to 0.
"Overflow" and "carry" are two different meanings of the concept, do not confuse. If you're not sure, check out the relevant chapters in the principles of computer composition course.
Second, the status control mark bit
The status control flag bits are used to control CPU operation, and they have to be changed by special instructions.
1. Tracking Mark TF (TRAP flag)
When the trace flag TF is set to 1 o'clock, the CPU goes into single step execution, that is, each execution of an instruction, resulting in a single step interrupt request. This method is mainly used for program debugging.
There is no specific instruction in the instruction system to change the value of the flag bit TF, but the programmer can use other methods to change its value.
2. Interrupt Allow flag if (interrupt-enable flag)
The interrupt allow flag if is used to determine whether the CPU responds to an interrupt request made by a masked interrupt outside the CPU.
However, regardless of the value of the flag, the CPU must respond to an interrupt request from an unshielded interrupt outside the CPU, as well as an interrupt request that is generated internally by the CPU.
Specific provisions are as follows:
(1), when if=1, the CPU can respond to the interrupt request of a masked interrupt outside the CPU;
(2) When if=0, the CPU does not respond to interrupt requests made by a masked interrupt outside the CPU.
The instruction system of the CPU also has special instructions to change the value of the flag bit if.
3. Direction Mark DF (Direction flag)
The direction flag DF is used to determine the direction in which the pointer register adjusts when the string operation instruction executes. The specific provisions are given in section 5th 2.11--string manipulation instructions.
In the instruction system of microcomputer, a special instruction is provided to change the value of the flag bit DF.
Three, 32-bit flag register increased flag bit
1. I/O privilege flag iopl (I/O Privilege level)
The I/O privilege flag is represented by a two-bit bits, also known as an I/O privilege level field. This field specifies the privilege level that requires the execution of I/O directives.
If the current privilege level is less than or equal to the value of IOPL, then the I/O instruction executes, or a protection exception occurs.
2. Nested task flag NT (Nested Task)
Nested task Flags NT is used to control the execution of interrupt return instruction Iret. Specific provisions are as follows:
(1), when nt=0, restore EFlags, CS, and EIP with the values stored in the stack, perform the normal interrupt return operation;
(2), when the nt=1, through the task conversion to achieve interrupt return.
3. Restart flag RF (Restart flag)
Restart flag The RF is used to control whether the debug failure is accepted. Rule: When Rf=0, said "accept" debug failure, otherwise refused.
After a successful execution of an instruction, the processor set the RF to 0, and when it accepts a non-debug fault, the processor will set it to 1.
4, virtual 8086-way flag VM (virtual 8086 mode)
If the value of this flag is 1, the processor is in the virtual 8086 mode of operation, otherwise, the processor is in a general protection mode of operation.

General Instructions for computer registers
I. Common directives
1. Generic data transfer instructions.
MOV transmits word or byte.
MOVSX the first symbol extension, then transfer.
MOVZX First Zero expansion, then transfer.
Push presses the word into the stack.
Pop the word pop-up stack.
Pusha the Ax,cx,dx,bx,sp,bp,si,di into the stack in turn.
POPA the Di,si,bp,sp,bx,dx,cx,ax to pop the stack in turn.
Pushad the Eax,ecx,edx,ebx,esp,ebp,esi,edi into the stack in turn.
Popad the Edi,esi,ebp,esp,ebx,edx,ecx,eax to pop the stack in turn.
Bswap switching the order of bytes in a 32-bit register
XCHG the interchange word or byte. (at least one operand is a register, and the segment register is not available as the operand)
CMPXCHG compare and swap operands. (The second operand must be an accumulator al/ax/eax)
XADD first exchange and then accumulate. (results in the first operand)
XLAT byte look-up table conversion.
BX points to the beginning of a 256-byte table, and AL is the index value of the table (0-255, i.e. 0-FFH); Return to AL for table results. ([Bx+al]->al)
2. Input and output port transfer instructions.
In I/O port input. (Syntax: In accumulator, {port number │DX})
Out of the I/O port. (Syntax: Out {port number │DX}, accumulator)
When the input/output port is specified by an immediate method, its range is 0-255; When specified by the Register DX, its range is 0-65535.
3. Destination address delivery instructions.
The LEA loads a valid address.
Example: LEA dx,string; Save the offset address to DX.
LDS transmits the target pointer and loads the contents of the pointer into the DS.
Example: LDS si,string; save segment Address: Offset address to ds:si.
LES transmits the target pointer and loads the contents of the pointer into ES.
Example: LES di,string; save segment Address: Offset address to ESDI.
The LFS transmits the target pointer and loads the pointer contents into FS.
Example: LFS di,string; add segment Address: Offset address to FSD.
LGS transmits the target pointer and loads the contents of the pointer into the GS.
Example: LGS di,string; add segment Address: Offset address to GSDI.
LSS transmits the target pointer and loads the contents of the pointer into the SS.
Example: LSS di,string; save segment Address: Offset address to SSDI.
4. Flag delivery instructions.
LAHF Flag Register Transfer, mount the flag in AH.
The SAHF flags register is transmitted and the AH content is loaded into the flag register.
PUSHF flag into the stack.
Popf flag out of the stack.
PUSHD 32-bit flag into the stack.
POPD 32-bit flag out of the stack.
Second, arithmetic operation instruction
Add addition.
The ADC carries a carry addition.
INC plus 1.
ASCII code adjustment for AAA addition.
The decimal adjustment of the DAA addition.
SUB subtraction.
SBB with borrow subtraction.
DEC minus 1.
NEC negation (minus 0).
CMP comparison. (two operands are subtracted, only the flag bit is modified, the result is not echoed).
The ASCII code adjustment of AAS subtraction.
The decimal adjustment of the DAS subtraction.
MUL unsigned multiplication.
Imul integer multiplication.
Above two, results echo Ah and Al (Byte operations), or DX and ax (word arithmetic),
The ASCII code of AAM multiplication is adjusted.
DIV unsigned division.
Idiv integer division.
Above two, result loopback:
Quotient Loopback al, remainder loopback ah, (byte operation);
or quotient loopback ax, remainder loopback DX, (Word arithmetic).
The ASCII code adjustment of the AAD division.
The CBW byte is converted to a word. (Extend the byte symbol in AL to AH)
The CWD word is converted to double word. (Extend the symbols in ax to the DX)
The Cwde word is converted to double word. (Extend the word symbol in AX to EAX)
CDQ double word extension. (Extend the symbols in the eax to edx)
Three, the logic operation instruction
And and operations.
or OR operation.
XOR is different or operation.
Not negate.
Test. (two operand and operation, only change the flag bit, do not echo the result).
SHL logical left shift.
SAL arithmetic left shift. (=SHL)
The SHR logic shifts right.
SAR arithmetic right shift. (=SHR)
ROL the loop left shift.
ROR loop right.
RCL the loop left through the rounding.
The RCR is shifted right through the carry loop.
The above eight shift instructions, the number of shifts can be up to 255 times.
When a shift is made, the operation code can be used directly. such as SHL ax,1.
When the shift >1 times, the number of shifts is given by the Register CL.
such as MOV cl,04
SHL AX,CL
Iv. sequence of instructions
Ds:si Source String Segment Register: source string variable address.
ES I Target string segment register: Destination string variable address.
CX Repeat Count counter.
Al/ax Scan value.
D flag 0 means that the SI and di should be automatically increment in the repetitive operation; 1 indicates that the amount should be automatically reduced.
The z flag is used to control the end of a scan or comparison operation.
MOVS string Transfer.
(MOVSB transmits characters.) MOVSW transfer Word. MOVSD transmits double word. )
CMPS string comparison.
(CMPSB compare characters.) CMPSW comparison word. )
SCAS string Scan.
Compare the content of the AL or ax with the target string, and the comparison results are reflected in the flag bit.
LODs loading a string.
Load elements (words or bytes) from the source string into either Al or Ax.
(LODSB transmits characters.) LODSW transfer Word. LODSD transmits double word. )
STOs Save the string.
is the inverse process of lods.
REP repeats when cx/ecx0.
REPE/REPZ when the zf=1 or comparison result is equal, and the cx/ecx0 is repeated.
REPNE/REPNZ when zf=0 or comparison results are not equal, and cx/ecx0 is repeated.
Repc when Cf=1 and cx/ecx0 are repeated.
REPNC when Cf=0 and cx/ecx0 are repeated.
v. Procedure transfer Instruction
1. Simple Conditional Transfer Instructions
JZ (or JE) OPR---------------result is zero transfer, test condition zf=1
JNZ (or jne) OPR--------------results are not zero-shifted, test conditions zf=0
JS OPR----------------------result is negative transfer, test condition sf=1
JNS OPR---------------------result is positive transfer, test condition sf=0
JO OPR---------------------Overflow transfer, test condition of=
Jno OPR--------------------not overflow transfer, test conditions sf=0
JP OPR---------------------results for even transfer, test conditions sf=1
JNP OPR--------------------results for odd transfer, test conditions sf=0
JC OPR--------------------have carry transfer, test conditions sf=1
JNC OPR--------------------No carry transfer, test conditions sf=0
2. Unsigned comparison conditional transfer instruction (the following directives are often the instructions behind CMP opd,ops to achieve a transfer based on the comparison result)
JB (or Jnae) OPD--------------less than or less than equals is transferred
JNB (or Jae) OPD---------------is not less than or greater than or equal to the transfer
JA (or Njbe) OPD---------------greater than or less than or equal to transfer
JNA (or Jbe) OPD---------------not greater than or less than or equal to transfer
3. Signed comparison conditional transfer directives
JL (or jnge)--------------less than or less than or equal to transfer
JNL (or Jge)--------------is not less than or greater than or equal to transfer
JG (or Njle)---------------is greater than or less than or equal to transfer
JNG (or Jle)---------------not greater than or less than or equal to transfer
Vi. calling subroutines and returning instructions
Call subroutine invocation instruction
RET subroutine return instruction
Vi. Other Directives
Offset--------------------to return a bias address
SEG--------------------return segment Address
EQU (=)--------------------equivalent statement
PURGE--------------------Dismiss statements
DUP--------------------manipulating numeric fields with the copy operator
Segment,ends--------------------Segment Definition directives
Assume--------------------segment address assignment directives
ORG--------------------Start offset address setting directive
$--------------------The current value of the address counter
PROC,ENDP--------------------Process Definition statements
Name,title,end--------------------Program Start concluding sentence
MACRO,ENDM--------------------Macro Definition directives
XLAT (TRANSLATE)--------------------code change instruction----
vii. conditions and signs
ZF 0 Flag-When the result is negative, sf=1, otherwise, sf=0.
AF auxiliary carry flag---the third digit in the operation process, set af=1, otherwise, af=0
PF parity flag------When the result operand is an even number of "1", pf=1, otherwise, pf=0
SF symbol Flag----When the result is negative, sf=1; otherwise, sf=0. Overflow Case exception
The CF carry flag-----The most significant bit to produce the carrying value, for example, when executing the addition instruction, the MSB has the rounding, the cf=1; otherwise, the cf=0.
of overflow flag-----If the operand result exceeds the range that the machine can represent, the overflow is generated and the of=1 is placed, otherwise, of=0
ENDM--------------------macro definition directives
XLAT (TRANSLATE)--------------------Code Change instruction----

Summary of assembly instructions

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