Summary of basic concepts of computer composition principle

Computer composition principle is the computer subject in favor of the hardware, I really did not learn, the only good notes are relatively complete. Ha ha. This course is really profound. Now the basic knowledge of the composition principle to share with you, I hope everyone in this course of learning less detours.

Introduction to Computer systems

The software-based machine is called a virtual machine, and a machine implemented by hardware and firmware is called the actual machine.
High-level language translation programs are compiled and interpreted in two ways.
The hierarchy of the computer system is from low to High:
(1) Micro-Program machine (level No. 0),
(2) Traditional machines (level 1th),
(3) Operating system machine (level 2nd),
(4) Assembly Language Machine (level 3rd),
(5) Advanced Language Machine (4th level),
(6) Application Language machine (level 5th).

In computer technology, an inherently existing thing or attribute, from a certain point of view but does not seem to exist, called transparency.
A complete computer system consists of two major parts: Hardware and software.
The computer hardware consists of five parts: the arithmetic device, the controller, the memory, the input device and the output device.
Storage consists of memory (cache, main memory (Rom,ram)) and secondary storage.
The host consists of the CPU (controller, operator, cache) and memory.
The auxiliary is called external memory. The information in the secondary memory can be read out and written, so the secondary is input.
Input devices, output devices, and secondary storage are located outside the host, known as peripheral devices, or peripherals. The peripheral is called an IO device because the function of the peripheral is to complete the input and output operation.
The system bus includes address bus, data bus, control bus.
The operator consists of the ALU (core), GR, PSW registers.
The controller is composed of PC, IR, instruction decoder, timing generator and Operation Controller.
System software includes:

(1) Language processing procedures,
(2) operating system,
(3) Service procedure,
(4) database management system.


Logical equivalence: Software and hardware are functionally equivalent, and the same functionality can be implemented either with software or hardware or firmware. In principle, the software implementation of the function can be completely done with hardware or firmware, the same, the hardware implementation of the logic can also be done with software.
Hardware-implemented features have high execution speed, relatively high cost, and hardware is not easy to change, flexibility is also poor. Usually hardware to achieve some of the most basic functions, software implementation of some more complex functions.
Computational methods and operators

Sign bits add forward-generated carry to throw away.
Positive overflow: Two positive numbers added, if the result of the operation is greater than the maximum number of positive number the machine can represent.
Negative overflow: Two negative numbers are added, if the result of the operation is less than the minimum negative number the machine can represent.
Fixed-point number (fixed-point integer, fixed-point decimal) method of judging overflow:

Single Sign bit method. When the number of symbols is added together, the sign bit of the result is different from the sign bit of the addend and addend when overflow occurs.
Carry Judgement method. Overflow occurs when the forward value of the symbol bit is different from the forward value of the mantissa's highest bit.
Double sign bit method. The two sign bits of the number are considered to be part of the number of participating operations, and the highest sign of the result is the forward-generated carry to be discarded. If the double sign of the result of the operation is the same, that is 00, 11 o'clock, the result does not overflow; If the double sign bit of the result is different, i.e. 01, 10 o'clock, the result of the operation overflows. 01 means positive overflow, 10 means negative overflow.

A multiplication of the original code: two n decimal places, to be n times Plus, n right shift.
Logic is not a bitwise negation. (Note logical non-symbols)
Logic Plus is logic or. (Note that there are two kinds of symbols)
Logical multiplication is logical and. (Note that there are two kinds of symbols)
Code spacing: Determined by at least a few bits between any two legal codes. If there is only one difference between any of the two legal codes, the code distance is 1.
Reasonable increase of the code distance, can improve the ability to find errors.
Parity check code is a kind of least cost, can find the data of an error in the code, often used for memory read and write inspection.
Implementation principle: Add a redundant bit in each set of code code, so that the code distance from 1 to 2. If an odd number of bits in the legal code has an error, the encoding becomes illegal. The increased redundancy bit is called the parity bit.

Parity codes can only find one error or odd number of dislocations, but cannot determine which one, so there is no error correction capability. You cannot find an even number of dislocations.

Storage System

Memory is used to store programs and data.
A storage element (storage bit) can store one binary code. This binary code is the smallest storage unit in memory.
Several storage bits form a storage unit, and a storage unit can store a machine word or a byte. The storage unit that holds a machine word is a word storage unit, and a byte storage unit is a byte storage unit. The corresponding storage cell address is called the word address and the byte address.
Memory Classification:

Divided by storage media: Semiconductor memory (main memory), magnetic surface memory (disk), optical disk memory (CD).
By Access mode: Random memory (semiconductor memory), sequential memory (tape), semi-sequential memory (disk).
Read-only memory (ROM), read-write memory (RAM).
Semiconductor memory by Read/write function: ROM, RAM
According to the information of the preservation of: volatile memory (RAM), nonvolatile memory (ROM).
According to the role of the computer: main memory, cache, secondary storage, control memory

The main basis of the storage hierarchy design is the local principle of the program. Including time locality and spatial locality.
Level Three storage: cache, main memory, secondary memory.
Ram can be stored in operation for long periods of time to store information in SRAM and DRAM. (Note: When the power is dropped, the stored information disappears and is volatile memory.) ）
SRAM uses a bistable trigger to store information, and the information is not lost as long as the power is constant.
The DRAM uses the capacitance to store the charge to hold the information and to charge the capacitor periodically to save the information.
SRAM speed is fast, but the integration is low, power consumption is large. DRAM instead.
Mrom: Masking ROM
PROM: Programmable ROM
EPROM: UV Erase programmable ROM
EEPROM: Electro-erase programmable ROM
Capacity expansion method of semiconductor Memory: Word extension method, bit extension method, word-extension method
Bit extension method: Extend the word length with multiple memory chips.
Word extension method: Increase the number of words in the memory.
High-speed memory has dual-port RAM (accessed by address), multi-Module interleaved memory (accessed by address), and associated memory (accessed by content). Can increase the data transfer rate between the CPU and main memory.
Dual-port RAM the same memory has two sets of independent read-write control circuits. It is a high-speed memory because of its independent operation in parallel.
Multi-module interleaved memory for parallel access to improve memory bandwidth. (Parallel operation of each module.) ）
Two ways of organizing memory modules: Sequential mode, cross mode.
The basic principle of the associated memory is to retrieve the memory by retrieving a portion of the contents of the storage unit as a retrieval item, and reading the contents of the corresponding storage unit into the readout.
Cache from the function, is the main memory buffer memory, composed of high-speed SRAM, all functions are implemented by hardware. The cache is transparent to both the system programmer and the application staff.
The data exchange between the CPU and the cache is in words, and the data exchange between the cache and main memory is in blocks.
Focus: The working process of the cache. Whenever a memory address is given, it is necessary to determine whether the access word is already in the cache through the main memory-cache address image transformation mechanism. If in the cache (cache hit), the address image transformation mechanism transforms the main memory address to the cache address to access the cache, if not in the cache (cache misses), the resulting cache block invalidation, it is necessary to access the main memory in the path of the block into the cache, and sent directly to the processor. If the cache is not already loaded, a cache block conflict occurs and the corresponding replacement algorithm is used to call up the block and modify the address image table.
Multi-Module interleaved memory is used in main memory system with cache.
The cache access priority is higher than the channel and CPU.
Cache Performance Parameter Calculation!
Address image transformation for cache and main memory (understanding)

Fully-linked images (Hardware autocomplete): Any piece of main memory can be placed anywhere in the cache. The probability of conflict is lowest. Cache space utilization is highest.
Direct image (Hardware AutoComplete): Each block in main memory can only be imaged to the only location in the cache. The main memory space according to the cache space into the area. The probability of conflict is high. Cache space utilization is low.
Group-linked images: Direct image between groups, fully-connected within groups.
Instruction System

Command System performance requirements

Completeness of
Effectiveness
Regularity of
Compatibility

According to the number of instruction address code, divided into 0 address instructions, an address instruction, two address instructions, three address instructions
The number of bits in the opcode determines how many different function instructions are. The more bits you have, the more functionality you can express.
Instruction operation code two encoding format: equal length operation code, variable length operation code (Huffman code, extended operation code)
The addressing method is the way to find an effective address for an instruction or operand.
Addressing method of instruction (simple) data addressing method (complex)
How to address an instruction

Sequential addressing: When a program is executed, the next instruction to be executed is the next one (PC) that is executing the instruction in the program.
Jump addressing Mode

How operands are addressed

Implicit addressing
Immediate addressing
Register Direct addressing
Register Indirect Addressing
Direct addressing
Indirect addressing
Relative addressing
Base Address addressing
Variable address addressing
Automatic incremental decrement addressing
Stack addressing




Implicit addressing: Some types of directives do not clearly give the address of the operand, but implicitly the operand given by the accumulator.
Immediate addressing: The form address of the instruction gives the operand itself.
Register Direct addressing: Understanding
Register indirection: The content of the Register is the valid address of the operand in main memory, and the content of the register is the real operand. (compared to register direct addressing, the number of operands directly addressed by the Register is in the register; the operand of the Register is indirectly addressed in memory.) ）
Direct addressing: Understanding
Indirect addressing: Understanding
Relative addressing: relative to the PC. The effective address of the operand in main memory equals the content of the PC plus the amount of displacement in the instruction.
Base Address: For the base register. The effective address of the operand in main memory equals the content of the base register plus the amount of displacement in the instruction.
Addressing: For the variable-address register. The effective address of the operand in main memory equals the content of the variable address register plus the amount of displacement in the instruction.


CISC mostly uses micro-program control. The use of the various instructions in the CISC is quite wide, the most commonly used are relatively simple instructions, accounting for only 20% of the total number of instructions, but the frequency of occurrence in the program accounted for 80%, which means that hardware-supported instructions about 80% is rarely used.
RISC simplifies controller design by streamlining the instruction system, increasing the capacity of on-chip registers and caches, adding floating-point arithmetic components, and improving processor performance with pipelined technology.
RISC is dominated by hard-wired control.
The decoupling Cisc/risc uses neither pure RISC nor classical CISC, but a hybrid cisc/risc architecture.
In the development of the instruction system there are two different directions, namely CISC and RISC, they all have their own merits and demerits. With the advent of decoupling cisc/risc and post-RISC, the structure of the two systems of RISC and CISC has been calmed down to a great extent, both from the opposing camp reference a lot of concepts and techniques, the two technologies gradually blending, structural differences are gradually blurred.


Cpu

Once the program is loaded into memory, the central processing unit can automatically and individually take instructions, analyze instructions and execute instructions.
CPU Basic functions:

Command control
Operation Control
Time Control
Data processing (This is the most basic function)

Basic CPU Composition

Controller
Arithmetic device
Cache, with instruction cache and data cache

Primary registers in the CPU

Pc. Program counter, instruction address register, instruction pointer.
IR. Instruction Register.
Ar. Data address Register
Gr. General purpose Registers
PSW. Status Word Register

When the CPU takes the instruction, the contents of the PC are fed into the instruction cache, the corresponding storage unit is selected after the address decoding, an instruction is taken out and the instruction code taken out is sent to IR, and the value of the PC is automatically modified to form the address of the next instruction.
The purpose of the instruction register is to save an instruction that is currently executing. When interpreting an instruction, first remove an instruction from the instruction cache based on the value of the PC and send it to IR. During the execution of this instruction, the content of the instruction register remains constant until a new instruction is removed and sent to IR.
The instruction decoder is used to decode the opcode field in the instruction register.
AR saves the address of the data cache unit that is accessed by the current CPU.
The part that generates the control signal and establishes the correct data path is called the Operation Controller. According to the operation code and timing signal of the instruction, various operation control signals with time sign are produced to establish the correct data path.
Operation control signal Formation method:

Micro-programming Method (Micro-Program Controller)
Combinatorial logic Design Method (hard-wired controller)

The timing generator produces a set of timing signals, as well as a series of beat potential and beat pulse signals. The function is to control the signal implementation time of various operation control.
The instruction period is the time taken from the CPU to take the command address to take out this instruction and complete the execution.
The minimum time required to remove and execute any instruction is two CPU cycles.
The CPU cycle is also called the Machine cycle, which consists of several clock cycles. A clock cycle, often called a beat pulse cycle or a T cycle, is the most basic unit of processing operations.
The instruction period is expressed in block diagram language. A box represents a CPU cycle.
The instruction is interpreted on the same CPU structure, and the value period of all instructions is the same.
In terms of time, the take-command event occurs during the first CPU cycle of the instruction cycle, that is, the value period, and the data event takes place within a few CPU cycles after the value cycle, which occurs during the execution cycle.

Spatially, if the code taken out is an instruction, it must be sent to the instruction register, and if the code being fetched is data, it must be sent to the general register or to the address register.

The most basic system of timing signal is the electric potential-pulse system.
A beat potential represents the time of a CPU cycle, including several beat pulses.
The timing signal required to achieve timing control consists mainly of the beat potential and the beat Pulse. They form the timing system of the CPU.
The method of controlling timing signals of different operation sequences is formed, which is called Controller control mode.
Control mode of controller:

Synchronous control mode
Asynchronous control mode
Joint control mode
Manual control mode


Synchronous control mode is also called fixed timing control mode. The basic idea is to select the longest operating time in the part as a unified CPU cycle time, so that all components can start and complete operations within a single CPU cycle, while the number of CPU cycles required for the most complex instructions is the standard as the interpretation time for all instructions. That is, the interpretation of all instructions in the instruction has the same number of CPU cycles and clock cycles.
Asynchronous control mode is also called variable Timing control mode. The basic idea is: The system does not set up a unified CPU cycle number and the number of clock cycles, the components at their own speed needs to occupy time.
The basic idea of the micro-Program control: The operation of the signal into a so-called "micro-instructions", stored in a read-only memory. When the machine is running, a single read out these micro-instructions, so as to produce a full range of operational control signals required to control the corresponding execution parts to complete the prescribed operation.
There are two kinds of connection between the control part and the executing part, one is through the control line, and the other is through the status line.
Micro command: Control components through the control line to the execution of the various control commands.
Micro-operation: performs the operation of the part under the control of the Micro command.
Micro-operation is divided into compatibility and repulsion.
In a CPU cycle of a machine, a group of micro-commands that implement certain operations functions constitute a micro-instruction.
The operations performed within a CPU cycle are implemented by a micro-directive.
Micro-Instruction composition


Operation Control Fields
Sequential control fields: P field and direct Micro address composition

The function of a machine instruction is implemented by a sequence consisting of several micro-directives. This micro-instruction sequence is also called a micro-program.
To determine the micro-address method:

Counter mode
Multi-Way transfer method (design with combinatorial logic method)

Micro Program Controller composition

Control memory
Micro-instruction register (micro-address register, Micro-command register)
Address transfer logic

The control memory holds all the micro programs of the instruction system, which is read-only memory.
The micro-instruction register is used to store a micro-instruction message read out by the control memory. Where the micro-address register determines the micro-address of the next micro-instruction that will be accessed. The Micro Command register holds the Operation control field and the P field for a micro command.
Machine instruction and micro-directive relationship:

The function of a machine instruction is implemented by a sequence consisting of several micro-directives.
The machine instructions are stored in memory and the micro instructions are cured in the control memory.
Each CPU cycle corresponds to a micro instruction.

How to encode a micro command:

Direct notation
Coding notation (Note: only 2 of n times minus one)
Mixed notation

Micro-instruction format:

Horizontal micro-Instructions
Vertical Micro-directives

Horizontal Micro instruction: In one CPU cycle, one can define and execute several micro-commands in parallel Operation Micro-command.
Vertical micro-directives: each vertical micro-instruction can only complete one operation, including only one or two micro-operations.
A micro program written with a vertical micro-instruction is much longer than a micro-program written with a horizontal micro-instruction. is to use a longer micro-program in exchange for shorter micro-instruction structures.
The horizontal type micro instruction takes a short time to execute an instruction, and the vertical type micro instruction executes for a long time.
Micro-programming Technology:

Static Micro-programming
Dynamic Micro-programming

The control function of the microcontroller is realized under the direct control of the control memory and micro instruction register, while the hard-wired controller is implemented by the combination of Logic gate (gate circuit, trigger).
The duality of parallelism means:

Simultaneous sex
Concurrency of

Granularity is used to measure the amount of computation included in a software process, and the simplest method is to represent the number of instructions in the program segment.
The size of the granularity is divided into

Fine granularity: less than 500
Medium Particle Size: 500~2000
Coarse granularity: Greater than 2000

Parallelism hierarchy (varies by particle size):

Job level
Task-level
Routine or sub-program level
Loop and iteration levels
Statement and instruction level

The higher the level, the coarser the granularity of parallel processing, and the finer granularity of parallel processing at lower levels.
Parallel Processing Technology:

Time parallelism
Space parallelism
Time Parallel + space parallel

How the instruction is interpreted:

Sequential Interpretation method
Water Interpretation method

Three stages of the pipeline:

Establish
Full
Emptying

Three types of water interpretation Related:

Resource-related
Data related
Control-related

56. Calculate throughput rate, speedup ratio, efficiency.
Bus structure

The bus is not just a set of transmission lines, it also includes a set of rules (protocols) for managing the transmission of information.
Characteristics of the bus:

Physical properties
Functional characteristics
Electrical characteristics
Time characteristics

The width of the address bus indicates that the bus has direct access to the memory's address space range.
The width of the data bus indicates the number of bits of data that can be exchanged when accessing a memory or peripheral.
The location of the bus relative to the CPU is divided into:

Internal bus
External bus

The external bus is divided by function:

Local bus
System bus
Communication bus

Bus by function divided into:

Address bus
Data bus
Control bus

According to the position of the bus in the microcomputer:

In-machine bus
Out-of-machine bus

Transmission of bits in the bus by data:

Serial Bus
Parallel bus

The bus is divided by the direction of information transmission:

One-way bus
Bidirectional bus

Input/output system

The input and output systems include:

Input
Device Controller
Hardware and software for input and output operations

The program that serves the event is called an Interrupt service program or interrupt handler.
An interrupt is a process that the CPU inserts into another program during the execution of the current program due to hardware or software reasons. Interrupts caused by hardware causes are unpredictable and random. Soft interrupts are arranged in advance.
Any device or event that can cause disruption is a source of interruption.
The interrupt source requests an interrupt request to the interrupt system, which is called an interrupt.
The 4 stages of an interrupt process:

Interrupt Request
Interrupt response
Interrupt Handling
Interrupt return

When dealing with an interrupt request in a certain level, it is not possible to interrupt its processing with a sibling or lower-level interrupt request than its advanced interrupt request. After the response and processing, continue to process the original interrupt request.
An interrupt request that has not been allowed is called an interrupt is masked.
The mouse and keyboard are connected in an interrupted manner.

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Summary of basic concepts of computer composition principle