Summary of questions and answers provided by Altera Forum

Link: http://group.ednchina.com/56/31122.aspx

 

Summary of questions and answers provided by Altera Forum

 

I can't afford losing any of these invaluable information anymore! It is not too late if I start reading and collecting them from now on. I will look the threads through everyday as I do with my Hotmail e-mails and eetimes rsss.

It's all about timing:

Sun Nov 01 2009 17:17:32 GMT + 0800 signal transfer in different clock domains
Sun Nov 01 2009 16:53:26 GMT + 0800 implementation and timing of Reset Circuits
Sun Nov 01 2009 16:46:41 GMT + 0800 timequest & output delay problem "I 've found it easy to totally get wrapped up into equations and lost in the details ."
Sun Nov 01 2009 16:39:19 GMT + 0800 PLL compensation warning still not quite clear about this. Need to do a experiment myself.
Sun Nov 01 2009 16:37:35 GMT + 0800 I need a low jitter clock MUX in logic cells I have collected some clock MUX circuits too. Planning on a blog post about these tricky designs someday.
Sun Nov 01 2009 16:36:16 GMT + 0800 understanding recovery and removal in timequest will study it carefully when I have time.
Sun Nov 01 2009 16:35:14 GMT + 0800 ripple and gated clocks: clock dividers, clock muxes, and other logic-driven clocks this one really helps. It guided my recent work to a success!

On the boundaries:

Sun Nov 01 2009 17:08:20 GMT + 0800 how to sample Io pin using SignalTap 2 logic analyzer? Need to do some experiments myself.
Sun Nov 01 2009 17:06:40 GMT + 0800 LVDS simulation of Stratix 4 using CST design studio Can anyone help him/her/me?
Sun Nov 01 2009 17:04:11 GMT + 0800 what kind of pad does the Quartus select when I configure the I/O as single-ended
Sun Nov 01 2009 17:01:12 GMT + 0800 Differential Pair and single-ended pins in hsmc of stratixiii 3sl150 Kit
Sun Nov 01 2009 16:55:36 GMT + 0800 how to connect PLL output to default pin what we can do or what we cannot do with the plls/clkctrls are never clear until we reached the P & R stage. isn' t this inconvenient?

Call me a "flow guy ":

Sun Nov 01 2009 17:15:04 GMT + 0800 how to maximize license utilization? Help myself!
Sun Nov 01 2009 17:03:16 GMT + 0800 log files generated by Quartus. Can anyone help him/her/me?
Sun Nov 01 2009 16:50:47 GMT + 0800 handling Quartus executable return codes I 've long been planning on a blog post about how to control the compilation flow within TCL.

Tricks:

Sun Nov 01 2009 17:21:42 GMT + 0800 how to extract 1bit from a bus in a block dimo-/ schematic File
Sun Nov 01 2009 17:12:13 GMT + 0800 x_on_violation_option