Summary of solutions to the CDC Problems

CDC (data transfer between different clocks) is the biggest headache in ASIC/FPGA design. CDC itself is divided into synchronous clock domain and asynchronous clock domain. Note that the synchronous clock domain refers to the clock domain with a certain relationship between the clock frequency and the phase, not necessarily only the clock with the same frequency and phase is the synchronous clock domain. There is no relationship between the two clocks in the asynchronous clock domain. Assume that the data is transmitted from clk1 to clk2.

During single-bit transmission, the synchronous clock domain can be deduced because the frequency and phase relationships are known. Therefore, the CDC problem can be solved without using additional hardware circuits,You only need to keep the source data in the clk1 end long enough.. There are two advantages for keeping it long enough: even if there is a sub-steady state, the data can be stabilized after the two clk2 clock cycles, so as to get the correct results. It can also prevent data loss because the frequency cannot keep up.

When a single bit is transferred,When transmitting asynchronous clock domains, additional circuit modules (synchronizers) must be used to ensure correct data transmission.. The most basic synchronization is the level synchronization of the dual lock structure, and the rest of the synchronization are derived from it. The principle of the synchronization is to save data for at least two cycles in the clk2 clock to eliminate the sub-steady state. Of course, the synx can solve the synchronization problem of the asynchronous clock domain. It can also solve the problem of synchronizing the clock domain. After all, the synchronous clock domain is simpler.

In the actual circuit design, no matter whether you are synchronizing the clock domain or asynchronous clock domain, as long as the data is transmitted between different clocks, the synchronization structure is added, this is of course a solution to laziness. Pulse synchronization is such a omnipotent structure,For single-bit cross-clock domain transmission, pulse synchronization is enough.There is no need to distinguish between the clock and the high frequency or the low frequency. After all, few people can grasp such details.

For multi-bit transmission, the single-bit transmission method is not supported. The reason is that when a single bit is transferred,It cannot be determined whether the data is valid after one clk2 clock cycle or after two clk2 clock cycles.. Therefore, the single-bit synchronization mechanism is used for each of multiple bits, which may result in the output of some incorrect intermediate states. For multi-bit transmission, only handshake signals or asynchronous FIFO are allowed.

 Summary:

1. In theory, we only need to keep the source data for a long enough time (the two cycles of clk2) for leaflet BIT data between related clocks;

2. If there is no relationship between the clock and the leaflet BIT data, you must use a synchronization device;

3. The pulse synchronization can solve this problem no matter whether the clock is connected to a single bit for transmission;

4. Multi-bit transmission only supports handshaking or asynchronous FIFO;

5. Low-frequency data collection at high frequencies. To prevent data loss, the source data should be slowed down to maintain more cycles. High-frequency data collection at low frequencies is not required, however, the results obtained from high-frequency low-frequency mining may have a lot of redundancy.