SWJTU Computer Composition Experiment C-experiment eight instruction analysis and execution _ computer

Experimental purposes, the description of experimental instruments, equipment, etc. see "Computer composition Experiment C" experiment and Curriculum Design Guide.

Brief comments: This thought very simple, until my naked eye DEBUG8 an hour later, do not think so, just now someone pointed out the error, and then changed well.

Using software: Quartus II 9.0 SP2

The experiment also uses ROM, although the experimental instructions are written on RAM, but I think it may be wrong.

This ROM contains 3 instructions, so I only set up a 4*16bit rom,16bit binary instruction, which translates to hexadecimal

7180 8c00 74c0 (the future may be revised, is not this difficult to say)

Notice here that the instructions given in the instruction sequence are given in mnemonics, with a discrepancy in order and instruction format.

I originally understood the R1 xor R2-> R3, but the correct one should be R1 <-xor R2

The original bug disappears after the instruction function has been modified.

To establish a MIF file here is no longer to repeat, if necessary can refer to

http://blog.csdn.net/uranus1024/article/details/72830168

Master Module Code:

===================== second Update, new pause control and control end ======================

LIBRARY IEEE; Use IEEE.
Std_logic_1164.all; Use IEEE. std_logic_unsigned.
All; Use IEEE. Std_logic_arith.

All;
           ENTITY zhiling is PORT (Clk,we,kg,control:in std_logic;
           Wtr,pc_in:in std_logic_vector (1 Downto 0);
           Inr:in std_logic_vector (3 Downto 0);
           Command:in Std_logic_vector (Downto 0);
           Pc:buffer std_logic_vector (1 Downto 0);
           Sel:buffer std_logic_vector (2 Downto 0);
Seg:buffer Std_logic_vector (7 Downto 0));

End ENTITY zhiling;
        Architecture one of the zhiling is SHARED VARIABLE cx,cy,cz,op,r1,r2,r3,r4:std_logic_vector (3 Downto 0);
        SHARED VARIABLE x:std_logic_vector (4 Downto 0);
        SHARED VARIABLE rx,ry,rz:std_logic_vector (1 Downto 0);
        SHARED VARIABLE times:std_logic_vector (9 Downto 0);
        SHARED VARIABLE state:integer RANGE 0 to 2;
    SIGNAL clk2:std_logic; Begin PROCESS (CLK2) BEGIN if CLK2 ' EVENT and clk2= ' 0 ' THEN IF kg= ' 0 ' THEN Case WTR (1 Downto 0) are when "a" => r1:=inr;
                        When "=>" R2:=INR;
                        When "ten" => r3:=inr;
                        When "one" => r4:=inr;
                    When others => NULL;
                End case; 
                            elsif kg= ' 1 ' and control= ' 1 ' THEN if state=0 THEN if we= ' 0 ' THEN
                        pc<=pc_in;
                            ELSE IF pc = "Ten" THEN pc <= "00";
                            ELSE pc<=pc+1;
                        End IF;
                        End IF;
                    State:=1;
                    End IF;
                        IF state=1 THEN Op:=command (Downto 12);
                        Rx:=command (one downto 10); Ry:=command (9 DowntO 8);
                        Rz:=command (7 Downto 6);
                            Case RX (1 Downto 0) are when "=>" CX:=R1;
                            When "=>" CX:=R2;
                            When "ten" => cx:=r3;
                            When "one" => cx:=r4;
                        When others => NULL;
                        End case;
                            Case RY (1 Downto 0) are when "a" => cy:=r1;
                            When "=>" CY:=R2;
                            When "ten" => cy:=r3;
                            When "one" => cy:=r4;
                        When others => NULL;
                        End case;
                            Case RZ (1 Downto 0) are when "=>" CZ:=R1;
                            When "=>" CZ:=R2;
                            When "ten" => cz:=r3;
        When "one" => cz:=r4;                    When others => NULL;
                        End case;
                    state:=2;
                    End IF;
                        If state=2 THEN if op= "0111" THEN cx:=cz XOR CY;
                        elsif op= "1000" THEN cx:= ' 0 ' & CY (3 Downto 1);
                        End IF;
                            Case RX (1 Downto 0) are when "=>" R1:=CX;
                            When "=>" R2:=CX;
                            When "ten" => r3:=cx;
                            When "one" => r4:=cx;
                        When others => NULL;
                        End case;
                            Case RY (1 Downto 0) are when "a" => r1:=cy;
                            When "=>" R2:=CY;
                            When "ten" => r3:=cy;
        When "one" => r4:=cy;                    When others => NULL;
                        End case;
                            Case RZ (1 Downto 0) are when "=>" R1:=CZ;
                            When "=>" R2:=CZ;
                            When "ten" => R3:=cz;
                            When "one" => R4:=cz;
                        When others => NULL;
                        End case;
                    state:=0;
                End IF;     
            End IF;
        End IF;
        End PROCESS;
                PROCESS (CLK) BEGIN IF CLK ' EVENT and clk= ' 1 ' THEN times:=times+1;
                IF times= "0" THEN clk2<=not (CLK2);
                End IF;
                Sel<=sel + 1;
                    Case SEL (2 Downto 0) are when "=>" x:= "11111";
                    When "=>" x:= "11111";
                    When "001" => x:= "11111"; WHEN "010" => x:= "11111";
                    When "011" => X (4 downto 0): = ' 0 ' &R1;
                    When "=>" X (4 Downto 0): = ' 0 ' &R2;
                    When "=>" X (4 Downto 0): = ' 0 ' &R3;
                    When "=>" X (4 Downto 0): = ' 0 ' &R4;
                When others => NULL;
                End case;
                    Case X (4 Downto 0) are when "00000" => seg<= "00111111";
                    When "00001" => seg<= "00000110";
                    When "00010" => seg<= "01011011";
                    When "00011" => seg<= "01001111";
                    When "00100" => seg<= "01100110";
                    When "00101" => seg<= "01101101";
                    When "00110" => seg<= "01111101";
                    When "00111" => seg<= "00000111";
                    When "01000" => seg<= "01111111";
                  When "01001" => seg<= "01101111";  When "01010" => seg<= "01110111";
                    When "01011" => seg<= "01111100";
                    When "01100" => seg<= "00111001";
                    When "01101" => seg<= "01011110";
                    When "01110" => seg<= "01111001";
                    When "01111" => seg<= "01110001";
                When others => seg<= "00000000";
            End case;
        End IF;
End PROCESS; End one;

has been landfills, and classmates discussed a bit, bug fix.

Schematic diagram Reference:

Pin Lock Reference:

=============== the control end of the second update is not reflected in the schematic and PIN lock, please the reader to configure the =================

Pin locking may not be consistent with the reader's usage and is for informational purposes only.