System Verilog Learning Notes (i)

1.var/reg and Bit/logic

Vary
Reg--> is used to declare registers in Verilog HDL;
Var--> all the temporary resources in the SV are considered as variables, i.e. variable;
With:
Both Reg and VAR consume FPGA resources.
Note:
The REG keyword is retained in the A.SV, and Reg is equivalent to Var.
B.SV also uses the var keyword when declaring ram.
Example:
reg [3:0] RLED; Verilog
var [3:0] RLED; Sysverilog

2, physical characteristics register generally has 4 states, namely 0,1,x,z
Verilog hdl-->reg keywords are considered to be 4 states by default
The sv--> resource is staged as 2 states, and the key word is bit, i.e. 0 and 1;
The resource is staged as a 4-state, and the keyword is logic, or 0,1,x,z
(z--> is used to drive the IO port, mainly blocking the output;x--> used to establish the selector)
Example:
var bit [3:0] RLED; Temporary resources of sysverilog,2 State
var logic [3:0] RLED; Temporary resources of sysverilog,4 State

Note: If the driver is IO, choose logic, and if the data is staged, select bit

3, ALWAYS_FF and Always_comb
In Verilog, there are point-in-time events and instant events that correspond to timing logic and combinatorial logic, respectively [email protected] (along the sensitive list) and [email protected] (*)
In system Verilog, sequential logic and combinatorial logic are represented by ALWAYS_FF (along the sensitive list) and Always_comb respectively;

Example:
[Email protected] (Posedge CLK)//verilog
[Email protected] (Posedge CLK)//system Verilog

Example:
[Email protected] (*)//verilog
Always_comb//system Verilog

//-------------------------------------------------------------
var logic [3:0] RLED;

Always_comb//combination logical behavior declaration, output selector is a combinatorial logic
if (isstart[0]) RLED = LED_U1;
else if (isstart[1]) RLED = LED_U2;
else RLED = 4 ' dx;

Assign LED = RLED;

//-------------------------------------------------------------

4, 2003 System Verilog wire and VAR have bit (2 states) and logic (4 states), in 2005, the system Verilog abolished it, by default The wire is logic (4 states):
Wire donesig_u1//system Verilog or Verilog equivalence relation
Wire logic DONESIG_U1//system Verilog equivalence relation
Wire bit DONESIG_U1//error Wire Declaration

5. struct and typedef

Note: Different from the use of C-language constructs
typedef struct {bit l0,l1,l2,l3;} LED_STRUCT;//Custom Structure, led_struct

var led_struct rLED;
[Email protected] (Posedge CLK or Negedge rstn)
if (! RSTN)
Begin
rled.l0 = 1 ' b0;
RLED.L1 = 1 ' b0;
RLED.L2 = 1 ' b0;
RLED.L3 = 1 ' b0;

...
End
......
Assign

6. Struct and packed
The struct defined in 5 requires a separate assignment for each member, when the custom structure is declared with the packed keyword, which is defined as a bitwise operation.
The first [0] bit of led_struct is L0, and the [1] bit is L1:

tepedef struct packed{bit l3,l2,l1,l0;} Custom structure after led_struct;//packed

var led_struct rLED; A custom structure declared as a staging type rled
var bit [3:0] RLED; Equivalence relation

RLED <= 4 ' D0;

When a custom struct with packed declares a staging type, Led_struct declares a staging type named RLED, which has an equivalent relationship to the "var bit [3:0] RLED" declaration method, and RLED can assign values directly to all members.

7. Ram and Packed

reg [7:0] ram [3:0]; Verilog declares 4 8-bit wide RAM

var bit [width][words] name; Declaring an array-system Verilog
var bit name [width][words];//declaration memory (RAM)-system Verilog

Example:
var bit [3:0][3:0] Array; Create a two-dimensional array named array with a bit width of 4 and a word of 4
var bit ram [3:0][3:0]; Build ram with a bit width of 4 and a word of 4

var bit [][]array={4 ' b1000,4 ' b0100,4 ' b0010,4 ' b0001};//An array is assigned directly to the array, by default the initial value is 0

[Email protected] (..... negedge rstn)
if (! RSTN)
Begin
Array <= ' {default:0};//Global array assignment 0
...
End

[Email protected] (Posedge CLK or Negedge rstn)
if (! RSTN)
Begin
array[0]= 4 ' b0001; Assigning members individually
array[1]= 4 ' b0010;
array[2]= 4 ' b0100;
array[3]= 4 ' b1000;
...
End

var bit [3:0][3:0] Array
var bit [15:0] RData//Both are equivalent relationships, two-dimensional array can be viewed with one-dimensional rData

The array declaration of System Verilog consumes register resources instead of memory resources. For FPGAs, register resources are invaluable and are not suitable for storing large amounts of data, so pay attention when using them.

System Verilog Learning Notes (i)