Talking from virtual memory management: from virtual address to physical address...

The MMU Memory Management Unit is responsible for converting the virtual memory address to the physical memory address.

 

Later, when studying the page table, we can see that when a process requests access to its memory, it is the responsibility of the operating system to map the virtual address provided by the process to the physical address where that memory is stored. the page table is where the operating system stores its Mappings of virtual addresses to physical addresses. in this case, the operating system is responsible for converting the virtual memory address to the physical memory address.

 

Is MMU hardware or OS responsible?

 

In fact, they are all right and exist in modern computers.

 

See:

ATranslation lookaside Buffer(TLB) Is a CPU cache that memory management hardware uses to improve virtual address translation speed.

The TLB is typically implemented as content-addressable memory (CAM). The cam search key is the virtual address and the search result is a physical address.

 

Software TLB and hardware TLB

A software TLB or a software loaded TLB, is a TLB that relies on the operating system to load entries from the pagetable. instruction Sets of CPUs that implement TLB have instructions that allow loading entries into any slot in the TLB. the format of the TLB entry is defined as a part of the ISA.^{[1]The names of the two types of disks, namely.}

A hardware loaded TLB (or hardware modified ed TLB), like on x86, is designed to load entries from the pagetable invisibly to the operating system. filling the TLB with address translations is under the control of dedicated hardware. in fact, if the TLB were removed from the CPU (not that it is a good idea), the programs wocould exhibit no difference, doesn't that the time for executing them wowould increase. moreover, since it is invisible to the OS and the ISA, the format of the TLB entries can be defined as needed and this definition can change from CPU to CPU without causing loss of compatibility for the programs. processors with a hardware TLB may still require TLB flushing instructions, such as arm processors, whilst other processor may implicitly flush the TLB on certain operations, such as x86.

The itanium architecture provides an option of using either software or hardware managed tlbs.^[2]

 

By the way, continue to see Cam:

Content-addressable memory(Cam) Is a special type of computer memory used in certain very high speed searching applications. It is also knownAssociative Memory,ASSOCIATIVE STORAGE, OrAssociative array, Although the last term is more often used for a programming data structure. (Hannum et al ., 2004) several custom computers, like the Goodyear staran, were built to implement cam, and were referred toAssociative computers.

 

OK, continue readingAssociative array:

AnAssociative array(AlsoAssociative container,Map,Mapping,Dictionary,Finite Map, And in query-processingIndexOrIndex File) Is an abstract data type composed of a collection of unique keys and a collection of values, where each key is associated with one value (or set of values ).

 

Associative arrays are usually used when lookup is the most frequent operation. for this reason, implementations are usually designed to allow speedy lookup, at the expense of slower insertion and a larger storage footprint than other data structures (such as association lists ).

 

There are two main efficient data structures used to represent associative arrays, the hash table and the self-balancing Binary Search Tree (such as a red-black tree or an AVL Tree ). skip lists are also an alternative, though relatively new and not as widely used. b-trees (and variants) can also be used, and are commonly used when the associative array is too large to reside entirely in memory, for instance in a simple database.

 

For more, http://en.wikipedia.org/wiki/Associative_array