TCP/IP protocol processing is changed from "soft" to "hard"

In the face of the rapid growth of network bandwidth and speed, traditional TCP/IP protocol processing through software has become the bottleneck of high-performance network computing.
In the current Ethernet environment, TCP/IP protocol processing is implemented on the central processor through software. When the network speed reaches the level of G bit, the master CPU becomes increasingly busy, and most of the processing load comes from processing the TCP/IP protocol, for example, the validation of IP data packets, the reliability and consistency of TCP data streams. A large amount of protocol data also needs to be operated through I/O interruptions, constantly exchanging data between the Network Interface Buffer and the application memory, which greatly reduces the processing efficiency of the master CPU, the average wait time of application computing is increased. According to the analysis of the CPU's processing ratio to the network data stream, the CPU consumes 1Hz of processing performance for every 1 bit of network data processed, that is to say, 20 GHz CPU processing capability is required to run at full capacity to meet the processing requirements of 10 GB Ethernet data streams.

At the same time, because the TCP/IP protocol is currently processed using a general CPU and its supporting system structure, the main function of the CPU in this system is to perform general computing, rather than input and output operations. Therefore, with the rapid development of network bandwidth and speed, the speed of the network link is higher than the CPU's processing speed on the TCP/IP protocol stack, leading to the network bottleneck of the system's input and output systems.

TOE shares protocol processing load

To improve and optimize server performance in a high-speed network environment and reduce the processing load on network protocols, the TCP/IP Load Reduction Engine TOE and TCP/IP Offload Engine technologies have emerged.

The basic idea of TOE technology is to share the CPU's processing of TCP and IP protocols, and put the protocol processing process on hardware such as high-speed Nic or high-speed line card, this includes processing of TCP/IP, IP, UDP, ICMP, and other sub-protocols. The block-level data transmission of TCP/IP Based on TOE technology will improve the performance by more than 10% than the normal method.

The TCP/IP Protocol originally processed by software is placed on dedicated hardware to separate applications from the network, which greatly improves the CPU resource utilization of the application server in the 10G Ethernet environment, it can significantly improve server performance. For example, in the IP Storage Field, this technology is clearly used in the iSCSI protocol processing process.

For traditional NICs, processing a 32 KB file requires nearly 30 interactions with the host CPU, 20 packet exchanges, and 10 responses. However, after the TOE function is configured for the NIC, data packets and response signals are processed in the NIC. The data-to-Application Buffer interval switching is performed by hardware-based DMA, this frees up more CPU resources for application processing. It also reduces the load on the system I/O bus and memory bus, and reduces the processing latency of the application system. After integrating the TOE function, the traditional Nic uses the Session Layer interface to interact with the host at the transport layer, helping to process large files in the application in excess of 10 KB. TOE processing and traditional TCP/IP processing methods, as shown in.
Such as 3C996-T 3C996-T 10/100/1000 PCI-X server Nic 3Com, integrated with the basic checksum and interrupt processing function, can achieve two-way m to M data throughput. An ENI with Advanced TCP/IP processing functions, such as Alacritech's X 1 server and storage accelerator, can achieve two-way data throughput from MB to MB. The following table lists the test and comparison data of TOE technology.

Implementation Strategy: partial or full?

The TCP protocol processing process can be divided into the following parts: TCP connection process, data transmission and receiving process, connection maintenance process, and error management process. Therefore, based on the TCP load balancing policy, TOE technology can be divided into two types: partial and full function sharing. You can select based on application requirements.

Partial share is also known as data path share. Because the 10G Ethernet environment has a very good network link and packet loss rarely occurs, TCP connections are relatively stable for a long period of time, and a large number of protocol processing comes from the data sending and receiving process, therefore, by sharing the data sending and receiving process, the CPU can focus on reducing the processing pressure on data sending and receiving, and improving the processing performance of applications.

Full-function sharing is to share all the four processes of TCP processing, and completely release the master CPU's load on TCP processing. When there are many network connections, frequent TCP connection and disconnection will consume a huge amount of CPU resources. In addition, due to the uncertainty of the working status of the Peer end of the TCP connection, this will cause the CPU to promptly handle TCP connection errors.

In order to integrate TOE into the current network processing system, in addition to providing the TCP processing function in the network interface hardware, the TOE network driver software must also be loaded in the operating system, the application at the operating system core layer uploads and releases data at the application layer through this interface.

Implementation Scheme: board implementation or ASIC chip?

In terms of device implementation, the TOE solution can adopt two structures: the component structure and the dedicated ASIC chip.

The separation component TOE is built on a circuit board and has a structure close to a computer with an embedded processor or microprocessor), firmware, memory, data transmission bus, real-time operating system, and the PHY/MAC interface. Generally, the protocol processing function completed by the host CPU is changed to the TCP/IP protocol stack embedded in the real-time operating system. The TOE board implementation scheme has the advantage of great flexibility, the separation components are easy to change, and the firmware can be easily used to grade the ROM chip; the TCP/IP stack can be modified through the firmware upgrade method, to adapt to special processing environments.

The implementation scheme using dedicated ASIC chip is to integrate the processing functions of the Protocol into the customized chip. Because of the dedicated processing and storage chip, therefore, asic toe greatly improves the performance, but the disadvantage is that the hardware development and initial application costs are relatively high, and the programming capability, scalability, and flexibility are relatively poor. The programmable capability and processing performance of network devices are often in conflict. In order to further improve processing flexibility and ensure processing speed, another configurable ASIC chip is available, which contains programmable firmware, software can be dynamically updated with greater flexibility.

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