Test summary of Image acquisition system based on fpga+usb2.0-mt9m001

Test summary of Image acquisition system based on fpga+usb2.0-mt9m001

The system adopts the FPGA_VIP_USB_V102 Board test produced by layer waves

Board is divided into: core board, backplane, camera board

Core board adopts: Ep4ce10e22 (EO4CE6E22 compatible) as the main control

Base Plate adopts: CY7C68013A as USB transmission chip

Camera Board (MT9M001C12STM): Clock is provided by the FPGA, programmable 24M, 48M, or 12M

Camera interface ( standard interface, if using non-standard interface, you can follow this jumper )

Pin Assignment (you can also reassign pin definitions according to the actual situation)

The project uses Verlog programming (can modify the configuration file in the corresponding module, modify the camera register parameters to achieve the purpose of modifying the resolution)

1, modify the XCLK clock, you can modify the sub-frame rate

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Global Assignment
Assigno_cmos_xclk= sys_clk48;

2, modify the register parameters, you can modify the image resolution, need and host computer corresponding

5:lut_data <= {8 ' h03,16 ' d479}; Number of rows-1:480
6:lut_data<={8 ' h04,16 ' D639};//number of columns-1:640

Default download 640*480 resolution JIC file

USB firmware is independent of resolution and frame rate, firmware does not require any modifications by default

Frame rate test (measured, limit frame rate, in order to stabilize, can properly reduce the frame rate)

Test summary of Image acquisition system based on fpga+usb2.0-mt9m001