The advent of the hybrid programming age of software and hardware -- the cyclone V series was released

Just saw the news: Altera built Dual Arm Cortex-A9 FPGA released, did not expect the early prediction of Altera built-in hard core FPGA finally become a reality ------ after Xilinx released Qaq, altera finally had a real response; and the most exciting thing was that two arm Cortex-A9 was built in costdown cyclone, it seems that the future of mixed software and hardware programming has gradually become a reality-its cyclone version means that the price of FPGA will not be an obstacle, at the same time, the embedded hard core also makes the low performance that FPGA has been criticized more and more historical;

The new cyclone-V architecture is as follows:

In addition to the hardware multiplication units (also called DSP Blocks) for early cyclone, the new cyclone-V ), the biggest change is the addition of a hardware unit called HPS (hard Processor System), which is essentially different from the Nios kernel of early cyclone: the early Nias were completely FPGA-based "soft" CPUs. Therefore, they could not compete with modern hard core CPUs in terms of performance, more is to provide a low-cost and inefficient solution, while the essence of the new HPS system is truly hard core;

The new HPS has the following features:

• Using TSMC-28nm process flow, 1.1v core voltage.
• Built in dual-MHz ARMCortex-A9 hard core processor, supporting SMP;
• Each core processor has the following features:
  • 32 KB L1 Instruction Cache and 32 KB L1 data cache
  • YesSingle precision and Double Precision Floating Point operation unit of IEEE-754And 128-bit neon simp media Engine
• Coresighttm debugging and Tracking Technology
• KB shared L2 high-speed cache
• Multi-port SDRAM Controller, supporting DDR2, ddr3, lpddr1, lpddr2
• 8-channel DMA Control Unit
• QSPI Flash Controller
• DMA-supported NAND Controller
• SD/sdio/MMC controller supporting DMA
• Two 10/100/1000 tthernet controllers, supporting DMA
• 2OTG USBController, supporting DMA
• Two I2C Controllers
• Two 16550-uart Controllers
• Two SPI serial interfaces (SPI)
• 134 General IO; 3.3 V 16mA driver
• 7 universal timers
• 4 watch dogs
• 64 KB On-chip RAM

The released cyclone v Se series are as follows:

In addition, there are GX series and GT series for high-speed transceiver-this is not my concern;

Although HPS can work independently as an independent component, it can be closely connected through the high-performance arm AMBA axitm bus, and under the control of the program, you can use a dedicated 32-bit port to configure the FPGA architecture by the CPU;

Developed to support the new qsys IDE development environment released by Altera (should be a substitute for early versions of the system's systems ):

At the same time, the exciting virtual target development environment is also released recently: In my understanding, the development of the prototype can be completed through software before the actual hardware design is complete, these virtual targets are compatible with the actual hardware. In this way, you can perform preliminary verification on the PC at a low cost. After the actual hardware is complete, these codes can be easily configured on real hardware. The new virtual targets also support cyclone v Se, and their OS supports vxwork and Linux;

I am also studying the details of the specifications. However, this configuration is indeed very exciting for me. The only pity is that my cyclone-III development edition, the Board that only supports the Nios seems to have become old-fashioned. Apply the most fashionable sentence: Whether you believe it or not, the coming of the hybrid programming age of hardware and software, I believe it.