The difference of DDR2 DDR3 __ Test

the difference of DDR2 DDR3

• Further reduction in power consumption

The default voltage of DDR2 memory is 1.8V, and the default voltage of DDR3 memory is only 1.5V, so the power consumption of memory is smaller and the calorific value is correspondingly reduced. It is worth mentioning that DDR3 memory also added temperature monitoring, the use of ASR (Automatic Self-refresh) design, by monitoring the temperature of the memory particles, minimize the refresh of the new frequency to reduce temperature and power consumption. DDR3 800, DDR3 1066 and DDR3 1333 compared to DDR2 800 module, the average power consumption can be reduced by 25%, 29% and 40% respectively.

• Increased number of logical bank

To further speed up the system, the DDR3 employs 8 internal banks, and DDR2 employs 4 or 8 internal banks, allowing for faster popularity of high-volume, high speed modules.

• Point-to-Point transmission mode

At higher operating frequencies, the signal integrity of the module in the DDR3 is more stringent. At extreme frequencies, the path of the signal cannot be guaranteed to remain stationary, but there is a need to adjust to match each dram. The fly-by topology uses point-to-point transmission mode, and the address line and the single path of the control line replace the DDR2 T-conventional T-branch topology, which is directly connected to each DRAM from the memory controller.

· ZQ Calibration Function

In addition, a ZQ pin is added to the DDR3, and a 240 ohm low tolerance reference resistor is connected to the pin. This pin uses a set of commands to automatically verify the end resistance of the data output driver through the ODCE calibration engine on the chip. When the system sends this instruction, it will use the corresponding clock cycle (512 cycles after the power up and initialization) to recalibrate the conduction resistor and ODT resistor after exiting the refresh operation with a 256 clock cycle and 64 cycles in other cases.

• Reset Reset function

Resetting the reset feature is also a new and important element in DDR3, which also has an independent pin in memory. The DRAM industry has long demanded that this feature be added, and is now finally being implemented on DDR3. This pin will make the initialization of the DDR3 easier. When the reset command is in effect, the DDR3 memory stops all operations and switches to the smallest active state to conserve power. During reset, DDR3 memory shuts down most of the intrinsic functions, so both the data receiver and the transmitter will be closed. All internal programs will be reset, DLL delay PLL and clock circuit will stop working, and ignore any movement on the data bus. This will enable DDR3 to achieve the most energy-saving purposes.

and there are some of the more abstract differences:

one, DDR2 and DDR3 memory characteristics of the difference:

1, logical Bank number

The DDR2 SDRAM has 4Bank and 8Bank designs designed to cope with future demand for large-capacity chips. And DDR3 is likely to start with 2Gb capacity, so the starting logical Bank is 8 and is ready for the next 16 logical bank.

2, Packaging (Packages)

As a result of DDR3 added some features, in the pin aspect will be increased, 8bit chip using 78 ball FBGA package, 16bit chip using 96 ball FBGA package, and DDR2 60/68/84 ball FBGA package three kinds of specifications. And the DDR3 must be a green package and cannot contain any harmful substances.

3. Burst Length (Bl,burst)

Since the DDR3 is 8bit, the burst transmission cycle (Bl,burst Length) is also fixed to 8, whereas for DDR2 and early DDR architectures, bl=4 is also commonly used, and DDR3 adds a 4-bit Burst Chop (Burst mutation) pattern, That is, a bl=4 read operation combined with a bl=4 write operation to synthesize a bl=8 data burst transmission, then can control this burst mode by A12 address line.

4. Addressing sequence (Timing)

Just as the number of delay periods increases as the DDR2 from the DDR transition, the CL cycle of DDR3 will also improve compared to DDR2. The CL range of DDR2 is generally between 2 and 5, while DDR3 is between 5 and 11, and the design of additional delay (AL) is also changed. At DDR2, the range of Al was 0 to 4, while DDR3 had three options for Al, 0, CL-1 and CL-2 respectively. In addition, DDR3 also adds a new timing parameter-write delay (CWD), which is based on the specific frequency of the work.

second, compared with the DDR2 DDR3 has the advantages (table-type unbuffered DIMM):

1. Faster: prefetch buffer width from 4bit to 8bit, the core of the same frequency of data transmission will be twice times the number of DDR2.

2. More power: DDR3 module voltage from the DDR2 1.8V down to 1.5V, the same frequency than DDR2 more power, with SRT (Self-refresh temperature) function, the internal increase in temperature senser, The update rate (rasr,partial Array self-refresh function) can be dynamically controlled according to the temperature to achieve the power saving purpose.

3. Larger capacity: More bank number, in accordance with the JEDEC standard, DDR2 should be available to the Unit Yuan 4Gb capacity (that is, a single module can to 8GB), but at present many DRAM manufacturer's planning, DDR2 production may skip this 4Gb unit element capacity, In other words, a single DDR2 dram module, the maximum capacity will be only to 4GB. and DDR3 module capacity will jump from 1GB, currently planning a single module to 16GB also no problem (note: This refers to the retail assembly market dedicated unbuffered DIMMs, server with FB and registered not this limit).

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DDR3: The delay really went up. (Correcting everyone's misunderstanding)

	DDR3	DDR2
CL (CAS latency)	5/6/7/8/9/10/11	3/4/5/6
AL (Additional latency)	0/cl-1/cl-2	0/1/2/3/4
RL (Read latency)	Al+cl	Al+cl
WL (Write latency)	AL+CWL CWL=5/6/7/8	RL-1

DDR3 I/O frequency compared to DDR2 has multiplied, in order to ensure accurate data transmission at high frequencies, the overall DDR3 delay compared to DDR2 improved. This situation also occurs when DDR2 replaces the DDR, which reduces the benefits of increased memory frequency, and the current DDR3 is also unavoidable.

The CL value for the DDR2 is 3-6, while the DDR3 is in the 5-11 range: ddr3-800 (5-6), ddr3-1066 (6-8), ddr3-1333 (7-10), ddr3-1600 (8-11). There have also been changes in AL (Additional latency), with the range of Al at DDR2 0-4, while DDR3 al had three options, 0, CL-1 and CL-2 respectively. At the same time, the DDR3 wl (write latency) is also higher than DDR2.

Many days ago, Samsung's semiconductor memory products experts pointed out that the one-sided view of CL value is DDR3 delay performance than DDR2, is completely false ignorance of the concept. In fact, he notes, the memory latency of the ddr2-533 cl 4-4-4, ddr2-667 cl 5-5-5 and ddr2-800 in Jedec is 15ns.

Samsung experts said that to calculate the entire memory module delay value, but also need to calculate the frequency of memory particles. If the CL values of ddr3-1066, ddr3-1333 and ddr3-1600 are 7-7-7, 8-8-8 and 9-9-9 respectively, the operating frequency of the memory particles is counted, and the delay value should be 13.125ns (7*1000/533.33), 12.0ns and 11.25ns, compared to the DDR2 improvement of about 25%, so the CAS value as memory delay value is not correct.

Obviously, CL and latency values, which are two different concepts, a unit is a clock cycle, such as cl=5, indicating that CL value is 5 cycles, and Samsung experts said the delay value, is the absolute time of delay, the unit is NS, the higher the frequency, the natural one cycle of the absolute time used is also shorter. When we were still brooding over the DDR3 cl, the absolute latency was actually decreasing .

DDR3 Introduction

DDR3 (double-data-rate three synchronous dynamic random access memory) is a high-bandwidth parallel data bus used in the computer and electronic products field. DDR3 on the basis of DDR2 inheritance development, the speed of its data transmission is twice times DDR2. At the same time, the DDR3 standard can make a single memory chip capacity to expand to reach 512Mb to 8Gb, so that the use of DDR3 chip capacity expansion to the highest 16GB. In addition, the operating voltage of the DDR3 is reduced to 1.5V, which is about 30% less than the 1.8V DDR2. In the final analysis, the biggest technical support for these indicators comes from the upgrading of the chip manufacturing process, and the 90nm or even more advanced 45nm manufacturing process makes the same function MOS tube smaller, resulting in faster, more dense, and more power-saving technology improvements.

DDR3 's development cannot be said to be a smooth one, although the original standard was released in 2005 and applied to the Intel P35 "Bearlake" chipset in 2007, but it did not replace DDR2 as quickly as the industry had expected. This has also experienced a far-reaching financial crisis on SDRAM industry, not only make the DDR3 occupy the market slower, but also make DDR3 in the technology of the world's leading memory of the giant dream of the collapse, it is regrettable. Nevertheless, DDR3 is now the fastest maturing standard in the parallel SDRAM family, and the JEDEC standard provides the highest speed of DDR3 up to 1600mt/s (note, 1mt/s is 1 million transmission per second). Furthermore, memory vendors can produce DDR3 products that are faster than JEDEC standards, such as DDR3 products with a speed of 2000mt/s, and even reported that the maximum speed can be as high as 2500mt/s.

Working speed of memory
Memory technology from the development of SDR,DDR,DDR2,DDR3, transmission speed exponentially, in addition to the promotion of wafer manufacturing process factors, but also because of the use of double Data rate and prefetch two technology. In fact, whether it's SDR or DDR or DDR2, 3, the core clock inside the memory chip is basically consistent, 100MHz to 200MHz (except for overclocking memory produced by some manufacturers). The DDR-double data rate technology increases the speed of data transfer by one-fold over the SDR. As shown in the following illustration, the SDR transmits data only along the rise of the clock, while the DDR transmits data along the clock signal and down the same time. For example, the same 133MHz clock, DDR can achieve the 266mb/s speed of the digital transmission.

Double Data rate technology to speed up the rate of transmission, and the speed of data transfer inside the chip is achieved through the prefetch technology. The so-called prefetch is simply to address multiple storage units at the same time in a kernel clock cycle and transmit the data in parallel to IO buffer, and then transfer data in IO buffer at a higher outbound speed. This higher speed is achieved by double Data rate in DDR I, and because of this, the frequency of the DDR I external clock pins is consistent with the core frequency within the chip. As shown in the prefetch process of DDR I, a 16-bit memory chip transmits 2 16bit data from the kernel to an external MUX unit at a time, and then transmits this 2 x 16bit to the North Bridge or other memory controller respectively on the clock signal, along the lower two times. The whole process goes through exactly the same time as a kernel clock cycle.

     developed to DDR2, the chip kernel each prefetch 4 times times data to IO buffer, in order to further improve the outbound speed, Chip core clock and external interface clock (that is, we usually contact the clock pin clock) is no longer the same 1:, the external clock clock frequency into the kernel clock twice times. Similarly, DDR3 each time prefetch 8 times times the data, its chip clock frequency is the kernel frequency 4 times times, namely JEDEC Standard (jesd79-3) stipulation 400MHz to 800MHz, plus in the clock signal, the next jumps along the same time transmits the data, The data transmission rate of DDR3 reached 800mt/s to 1600mt/s. Specific to the speed of memory, we take pc3-12800 as an example, its use of ddr3-1600 chip core frequency of 200MHz, after prefetch clock signal frequency to reach 800MHz, and then after double Data After the rate chip data transmission rate is 1600 mt/s, the memory strip transmits 64 bits each time or says 8 byte data, 1600x8 obtains the 12800mb/s peak bit rate.

The following table lists the DDR3 chips and memory-bar-related parameters specified in the JEDEC standard (jesd79-3). It is to be explained that as mentioned earlier, not all memory products are fully compliant with the JEDEC standard, some manufacturers will produce faster DDR3 chips, in general, these chips from the chip detection process to filter out the frequency of the dynamic range of larger chips, or can be pressurized overclocking work chip.
 

The difference between

 DDR3 and DDR2
     data transfer rate is the most significant difference between DDR3 and DDR2, as described above. Let's look at other aspects of the difference.

In terms of power supply, the operating voltage of the DDR3 is reduced to 1.5V, in fact the JEDEC standard stipulates that 1.575V is the maximum safe operating voltage for DDR3. In addition, the standard also stipulates that the memory can withstand the safe supply voltage must be greater than 1.975V, of course, at this voltage, the memory bar may not work properly but not damaged.

The asynchronous reset signal is introduced in chip-level DDR3, which mainly provides two functions, one is to simplify the initialization process after the memory chip, the other is when the memory system into the unknown or uncontrolled state can be directly reset without power to restart.

In terms of interfaces, the common un-buffer memory strips, for example, DDR3 and DDR2 are 240 pins, with a uniform size but a different position for the slot, which is incompatible with the electrical properties due to different working voltages.
The biggest difference between DDR3 and DDR2 in system design is that DDR3 moves the terminal resistor of the clock, address, and control signal line from the computer board to the memory strip, so that no end resistors are required on the motherboard. In order to minimize the signal reflection, all control lines including the clock line on the memory strip are fly-by topological structure. At the same time, because of the fly-by's alignment structure, the control signal line reaches the length of each memory particle, which leads to inconsistent signal arrival time. This situation will affect the memory read and write process, for example, in the read operation, because the memory controller from the read command sent to each memory chip at different points in time, will cause each memory chip at different times to send data to the controller. To eliminate this effect, you need to compensate for time when you read and write memory, which will be done by the memory controller. The system framework of the DDR3 bus is shown in the following diagram, where the red line represents DQ, DM, and differential DQS signal lines, and the black line represents the clock, address and control signal lines, T represents the corresponding end-connection resistance.

DDR3 Test
JEDEC standard DDR3 test is divided into three aspects, namely: clock test, timing test and electrical performance test. Where the clock test mainly test the clock signal cycle, the parameters such as pulse width, periodic jitter, and continuous n-cycle cumulative error, and so on; Time series test the main test data read and write to establish and maintain the relevant parameter; Electrical performance test the main test signal integrity related indicators, mainly including the slope of the signal and direct/communication logic high/ Low electricity equality indicators. The complete DDR3 test project not only has a wide variety and involves the complex judgment process of signal reading and writing separation, manual measurement is not only time-consuming and laborious, but also difficult to guarantee the accuracy of measurement. In response to this, the Force Division has launched the latest QPHY-DDR3 automated testing software package, it will be a graphical interface to help users complete from the measured signal lap, signal acquisition and read and write separation, automatic testing and analysis to the final test report to generate this series of complete test work.