The effect of clock jitter of high speed ADC on signal-to-noise ratio and effective bit number

High speed ADC Clock jitter solution

The clock jitter of the high-speed ADC affects the SNR of the high-speed ADC, while the signal-to-noise ratio determines the effective range of the analog front-end input. Therefore, it is necessary to determine the effective input range of the analog front end, then determine the SNR that should be satisfied, and then deduce the clock jitter.

First, the relationship between the dynamic input range and the effective bit enob of the analog front-end

Assume that the maximum input amplitude of the ADC is VPP (Unit v), the number of resolution bits n bits, the number of significant digits enob bits.

The effective number of digits enob is the number of bits actually useful in the N-bit resolution of the ADC. N-bit ADC theory minimum resolution satisfies

However, if the noise signal of the ADC is greater than 1LSB, then not every bit in the N-bit representation of the ADC sample signal can represent the sampled signal, so the actual resolution number is less than n, and the actual resolution number is known as the significant number of digits enob. Therefore, for ADC, the more effective parameter is Enob, instead of N,ADC the actual minimum resolution should be:

The analog input dynamic range for the ADC is (Vppmin,vppmax), and the vppmin and Vppmax are calculated using the following formula

Amplitude width of analog input:

Vppmax-vppmin=6.02enob

The relationship between the effective bit enob, Snr, Nabi Sinad, total harmonic distortion THD

2.1. SNR

The definition of Snr is the ratio of the RMS of the signal amplitude to the RMS of the noise amplitude. Assuming that the signal amplitude RMS is s, the noise RMS is N, then

2.3, SINAD

Sinad is the ratio of the RMS of the signal amplitude to the mean of the square root of all other spectral components (including harmonics but not DC). Assuming that the signal harmonic amplitude RMS is n, then

2.2, THD

THD refers to the ratio of the RMS value of the fundamental signal to the mean of the square root of its harmonics (typically only the first 5 harmonics are more important). Assuming that 2 times, 3 times, and more than 4 harmonic wave distortion is HD2,HD3,HDN, the total harmonics distortion is D, then the THD can be solved with the following formula:

Some of the ADC's datasheet provide a value of THD, but there are some that are not directly supplied with the THD is worthwhile, and no THD is worth using HD2,HD3,HDN calculations.

2.4ENOB, SNR, SINAD, THD relationship

A definite relationship is satisfied between the letter Nabi and the significant number of digits:

So we can deduce the Sinad value that the ADC needs to satisfy according to the required Enob.

The definitions of Sinad, THD, and Snr can be derived from the following formulas:

The THD is that the ADC can be directly or indirectly obtained through the datasheet of the ADC, so we can deduce the condition that the SNR should meet in order to satisfy the demand sinad.

Third, SNR solution

The SNR of the ADC is mainly caused by three parts: quantization noise, thermal noise, jitter noise.

3.1. Quantization noise

When the ADC quantifies the sampled signal, it will produce some errors, from the quantization to the actual signal and the quantization of the error between the signal is maximum 0.5LSB. The quantization error is shown in the following figure:

Calculation formula of signal-to-noise ratio caused by quantization error:

3.2. Thermal noise

Thermal noise is an inherent noise of the chip, caused by sampling buffer noise, sampling switching impedance, etc., is a fixed value, the general ADC will give the signal-to-noise ratio of the thermal noise. If not given, it can be calculated using the following formula:

Nsd:noise spectral density or noise floordensity

3.3. Jitter Noise

Jitter noise is mainly caused by clock jitter and Aperture jitter.

The above two graphs describe the effect of clock jitter and aperture jitter on the sampling point, both of which will cause the sampling point offset, but at the end of the data processing, the default points are sampled in the ideal position, in the frequency domain will cause the dispersion of the signal frequency Another way to understand this is to have a certain deviation between the actual sample value and the ideal sample value for each sample point, which is equivalent to a noise superimposed on each point.

The signal-to-noise ratio of noise caused by clock jitter is calculated using the following formula

From the above two formulas can be derived from the signal-to-noise ratio and the sampling clock jitter inversely proportional to the input signal frequency, so the higher the frequency of the input signal, the jitter requirements of the clock signal more stringent.

3.4. Total noise

The total ADC noise is the sum of quantization noise and jitter noise. Quantization noise is often not considered, because many times the thermal noise is far greater than the quantization noise. When the signal frequency is low, the main consideration is the thermal noise, when the signal frequency is high, will consider the jitter noise

The total signal-to-noise ratio of the ADC is calculated using the following formula:

Iv. Examples of jitter solutions

4.1, AD9680 clock jitter solution

Ad9680:14 bit resolution number, aperture jitter 55fs, sampling frequency 1GHZ,THD value 80dBFS, thermal noise 67dBFS, calculated jitter, Snr_jitter, SNR_ADC, FIN, enob as follows:

The first picture is the relationship between jitter, Fin, Snr, red for snr_jitter, green for SNR_ADC, from top to bottom is different fin corresponding Snr, frequency is from 1MHz, to 501MHZ, step 50MHz.

The second picture is the relationship between jitter, Fin, Enob, and from the top down is the corresponding Snr of different fin, the frequency is from 1MHz to 501MHZ, step 50MHz.

As can be seen from the figure: the higher the fin, the greater the SNR, the smaller the enob, the greater the jitter, the greater the SNR, the smaller the enob. In order to ensure AD9680 better conversion performance, it is best to make the clock jitter less than 150FS, can guarantee more than 10 digits of the significant number.

5.2, ads54j54 clock jitter solution ads54j54:14 Bit resolution bit, aperture jitter 98fs, sampling frequency 500GHZ,THD value 80dBFS, thermal noise 66dBFS, calculated jitter, Snr_jitter, Snr_ The ADC, FIN, and enob are shown below:

The first picture is the relationship between jitter, Fin, Snr, red for snr_jitter, green for SNR_ADC, from top to bottom is different fin corresponding Snr, frequency is from 1MHz, to 251MHZ, step 50MHz.

The second picture is the relationship between jitter, Fin, Enob, and from the top down is the corresponding Snr of different fin, the frequency is from 1MHz to 251MHZ, step 50MHz.

4.3, ADS6445 clock jitter and AD9680 clock jitter comparison

From the Jitter solution results of the two chip, it is found that the higher the sampling frequency, the higher the signal frequency of the ADC the more stringent the clock jitter requirements. AD9680 in order to ensure better performance, need less than 150fs jitter;ad54j54 in order to meet good performance, need less than 300fs jitter.

By flipping through the datasheet of different ADCs, we find a rule of a parameter, the more the sample speed of the ADC, the smaller the aperture jitter. This parameter is intrinsic to the ADC itself and is related to the chip design. The same principle of aperture jitter and clock jitter affects ADC performance. For higher sampling rates, the chip development chamber designs smaller aperture jitter, which allows us to quickly estimate the size of the clock jitter. When the clock jitter is smaller than the aperture jitter, can get very good ADC performance, when the two similar, still can maintain a good performance, when the clock jitter is two or three times times the Aperture jitter, the performance is relatively good, when this ratio is larger, it is necessary to reference the frequency of sampling signal to specific analysis. Therefore, when designing the ADC clock, the jitter can be roughly set to within twice times the aperture jitter.