The DFF of VHDL

D-flip-flop with async reset or set

1 LibraryIEEE;2  Useieee.std_logic_1164. All;3 4 EntityFFD is5     Generic6     (7Resetval:Std_logic:='0'; --!SelectAsync Set/Async Reset8Clockfall:Boolean: = False--!SelectClock Edge9     );Ten     Port One     ( ARst:inch    Std_logic; --!Async Reset -C:inch    Std_logic; --!Clock -D:inch    Std_logic; --!Input theQ: out    Std_logic--!Output -     ); - EndFFD; -  + ArchitectureBeh ofFFD is -     SignalClock:Std_logic; --!Active Clock +  A begin at  -Gckr:ifClockfall =false Generate -Clock <=C; - End Generate; -GCKF:ifClockfall =true Generate -Clock <= not(C); in End Generate; -  toPFF:Process(Rst,clock) +         begin -             if(RST ='1') Then theQ <=Resetval; *             Else $                 if(Clock'Event and Clock ='1') ThenPanax NotoginsengQ <=D; -                 End if; the             End if; +         End ProcessPFF; A EndBeh

The DFF of VHDL