The Makefile of Linux

Makefile's role is to tell the make program how to compile and link the source code!

How make Works

When we enter only the Make command, the workflow is:
1. Make will find the file named "Makefile" or "Makefile" in the current directory;
2. If found, it will find the first target file in the file (target), in the above example, he will find "main" This file, and the file as the final target file;
3. If the main file does not exist, or if the file modification time of the following. o file that main depends on is newer than the main file, then make executes the command defined below to generate the main file;
4. If the. o file that main depends on also exists, then make will find the dependency of the. o file in the current file, and if found, generate the. o file according to the command (this is a recursive process);

If in the search process, there is a dependency on the file can not find the error, then make will exit directly, and error.

If in a dependency chain, for example: a relies on b,b dependent c,c D. Then when D is updated, make discovers that D will rebuild C newer than C, and so on, and eventually a will be updated.

Syntax composition of the makefile file

Basic form of construction:

1 target:prerequisites 2     Command3    command4...     

Description
Target: Can be any type of file, or it can be a label, or be called a "pseudo-target", this we'll talk about later.
Prerequisites: This is the file and target to generate the target.
Command: When prerequisites is newer than target, it executes the action defined here (any shell command)

is actually a file dependency processing, that is, the target target depends on the file in the prerequisites, and its generation rules are defined in the command. White point is that if any one or more of the files in the prerequisites is newer than the target file, command-defined commands are executed. This is the rule of makefile. is also the core content of makefile.

Using Variables in Makefile

We use scripting experiments to understand several forms of defining variables:

1 . Phony:target2 3var_0:=$ (VAR)4var_1=$ (VAR)5Var="Hello World"6var2:=$ (VAR)7Var="Hello world2"8var3="Hello world3"9var3?=$ (VAR)Tenvar_0+="ABC" Onevar_1+="ABC" A  - Target: - @echo $ (var_0) the @echo $ (var_1) - @echo $ (VAR) - @echo $ (VAR2) -@echo $ (VAR3)

$ make
Abc
Hello world2 ABC
Hello World2
Hello World
Hello world3

"=" direct assignment, more intuitive. It is worth saying that when the assignment is a variable, if the referenced variable does not exist, then the assigned value is an empty string.
": =" defers the reference variable, that is, make will find the value of the referenced var variable only if the VAR2 variable is used in the script.
The "? =" conditional assignment is called a conditional assignment because the variable is assigned only if it was not previously assigned.
The "+ =" Append assignment, the output of the above example is obvious.

The environment variables of the shell process can also be used directly in makefile, such as the ability to output @echo $ (PATH) in Makefile, and so on.

Make Auto derivation
Let me start by creating several files locally:

$ vim Lib1.h

1 #ifndef __lib1_h__ 2 #define __lib1_h__3void  lib1 (); 4 #endif

$ vim lib1.c

1 #include <stdio.h>2void  lib1 ()3{4     printf ("This islib1\n"); 5 }

$ vim Lib2.h

1 #ifndef __lib2_h__ 2 #define __lib2_h__3void  lib2 (); 4 #endif

$ vim lib2.c

1 #include <stdio.h>2void  lib2 ()3{4     printf ("This islib2\n"); 5 }

$ vim MAIN.C

1 " Lib1.h " 2 " lib2.h " 3 4 int Main (intChar *argv[]) {5    lib1 (); 6     lib2 (); 7     return 0 ; 8 }

$ vim Makefile

1 . Phony:clean2 3Cc=GCC4cflags=-O35objs=main.o lib1.o lib2.o6lib=libtest.a7bin=Main8 9 $ (BIN): $ (LIB) $ (bin). OTen$ (CC) $ (CFLAGS)-o [email protected] $ (BIN). O-l.-wl,-bstatic-ltest-wl,-bdynamic Oneecho $? A  -%.O:%. C -$ (CC)-c-o $*.o $*. C the  - $ (LIB): LIB1.O lib2.o -AR crv [email protected] $^ -  + Clean : -RM-RF $ (BIN) +RM-RF $ (OBJS) ARM-RF $ (LIB)

$ make

You can change your own code to test!

Say it. The role of phony. Phony behind the pseudo-target, that is, the goal is only to occupy a symbol of a name, regardless of whether there is a clean file in the current directory, no comparison is not up to date, as long as the execution of the command defined under the make Clean,clean target will always execute!

[Email protected]: Indicates the target file name
The first dependent name in the $<:prerequisites dependency list
$?: A collection of all new dependent file names that are more than the target, separated by a space
$^: All files that are dependent on the current target, it is not concerned that these files are newer than the target file. However, duplicate dependent filenames are removed. This can be useful when you need to output all of your dependent files to the screen
$+: Much like $^, also a collection of all dependent files, but it does not remove duplicate dependencies
$*: Matches the part before "%" in the target pattern

Good methods and techniques:
1. Introduction of external Makefile
2. Variable Value substitution
It is not impossible to create a new macro from an existing macro. For example, the macro SRC represents a series of source files, and you want to generate a corresponding target file for macro obj. To do this, you only need to specify OBJ = SRC, except for the difference in extension: obj = $ (SRC:.C=.O)

Trap:
1. Environment variable makefiles
2. Traps for Universal wildcard characters
3. Environment variable VPATH

This article will continue to polish and improve!

The Makefile of Linux