On the two "modify startup code & rewrite vector table" SRAM initialization & Set Nvic Interrupt table offset article, we set the interrupt vector table, initialized the RAM, and reset the address of the vector table, this article is a relatively important one, we will set the chip clock.
1. New CortexM3.h header File
Create a new CortexM3.h file in the. \devicecode\targets\native\cortexm3 directory and write the following code:
#ifndef _cortexm3_h_
#define _CORTEXM3_H_1
#include <cores\arm\include\cpu.h>
typedef volatile unsigned long VU32;
typedef volatile unsigned short VU16;
typedef volatile unsigned char VU8;
extern "C"
{
void Bootstrapcode_clocks ();
}
/*------------------------Reset and Clock control---------------------------*/
struct CORTEXM3_RCC
{
static const UINT32 c_base = 0x40021000;
static const UINT8 Flag_hsirdy = ((UINT8) 0x20);
static const UINT8 Flag_hserdy = ((UINT8) 0x31);
/****/volatile UINT32 CR;
static const UINT32 Cr_hsebyp_reset = ((UINT32) 0xFFFBFFFF);
static const UINT32 Cr_hsebyp_set = ((UINT32) 0x00040000);
static const UINT32 Cr_hseon_reset = ((UINT32) 0xFFFEFFFF);
static const UINT32 Cr_hseon_set = ((UINT32) 0x00010000);
static const UINT32 Cr_hsitrim_mask = ((UINT32) 0xffffff07);
/****/volatile UINT32 cfgr;
static const UINT32 CFGR_SYSCLK_DIV1 = ((UINT32) 0x00000000);
static const UINT32 CFGR_SYSCLK_DIV2 = ((UINT32) 0x00000080);
static const UINT32 CFGR_SYSCLK_DIV4 = ((UINT32) 0x00000090);
static const UINT32 CFGR_SYSCLK_DIV8 = ((UINT32) 0x000000a0);
static const UINT32 CFGR_SYSCLK_DIV16 = ((UINT32) 0x000000b0);
static const UINT32 CFGR_HCLK_DIV1 = ((UINT32) 0x00000000);
static const UINT32 CFGR_HCLK_DIV2 = ((UINT32) 0x00000400);
static const UINT32 CFGR_HCLK_DIV4 = ((UINT32) 0x00000500);
//Omitting part of the code ...
/****/volatile UINT32 apb1rstr;
/****/volatile UINT32 ahbenr;
/****/volatile UINT32 bdcr;
/****/volatile UINT32 CSR;
static void Initialize ();
static bool Getflagstatus (UINT8 Flag);
};
struct CortexM3
{
static CORTEXM3_RCC & RCC () {return * (CORTEXM3_RCC *) (size_t) (cortexm3_rcc::c_base);
};
#endif//_cortexm3_h_1