The principle, design and Verilog realization of counter

If the counter consists of n triggers, then the number of bits of the counter is N, and the maximum modulus that can be counted is 2 n power. The following is a synchronous binary addition counter circuit;

Drive equation: state diagram

The state equation (q0,q1 at this time is the last state value):

The following example is the design of the synchronous 4-bit 2-counter: The counter has the function of asynchronous zeroing, synchronous number, with clock end: CLK; terminal: s; 0 end: R; enable end: En; terminal: d[3:0]; output: Q [3:0]; carry end: Co.

Modulecounter (clk,co,q,r,s,en,d);inputClk,r,s,en;//clock, clear 0 end, terminal, enable endinput[3:0] D;//number of input terminalsOutputCo//Carry EndOutput[3:0] Q;//Counting output EndReg[3:0] Q;//4-bit count registerRegCo//1-bit carry register always@(PosedgeClk//clock rising edge triggerif(r)//determine if the 0 end is 1beginq=0;End //Yes, clear the Count register 0.Elsebeginif(s)//determine if the end of the set is 1beginQ=d;End//Yes, give the value of the input to the Count register.Elseif(en)//determine if the Enable End is 1beginQ=q+4'B1; Yes, q, add 1.if(q==4'b1111)//Determine if q is fullbeginco=1;End  //that's it. Carry End 1Elsebeginco=0;End  //no words carry end 0EndElsebeginq=q;End //Q Keep The original valueEndEndmodule

Timing Simulation Diagram:

When programming about blocking assignment and non-blocking assignment note points:

1. Blocking assignment operation with "=", blocking refers to the process statement (initial and always), the current assignment statement blocks the subsequent statement, that is, the subsequent statement must wait until the current assignment statement is completed before execution. When the assignment is real-time, after the calculation is immediately assigned to the left, and then the next sentence, the operation is serial, and in a always completed. Theoretically, it has only conceptual precedence over the subsequent assignment statements, and there is no substantial delay.

always @ (posedge  clk)beginx=next_x;y=x; End

When the "x=next_x" is executed, X is immediately to next_x, and the next sentence is executed after y=x, because the two statements have no delay (for the wire), resulting in "y=next_x".

2. Non-blocking assignment with <=, non-blocking means that in a process statement, the current assignment does not block subsequent statements, and all non-blocking statements are assigned values at the same time after entering the city.

When "x<=next_x" is executed, the execution of "y<=x" is not blocked. Therefore, the value of X in the statement "Y<=x" differs from the value of the statement "X<=next_x", and the value of X in the statement "x<=next_x" is the output value of the D trigger after a synchronous pulse, and the X of "Y<=x" is the initial value of the first D trigger.

In summary, the blocking assignment is performed on demand, and non-blocking assignment is performed in parallel.

In Verilog programming, keep in mind the following eight principles:

1) When the sequential circuit is modeled, it is assigned with a non-blocking value.

2) When the latch circuit is modeled, it is assigned with a non-blocking value.

3) The block assignment is used when building a combined logical model with always blocks.

4) When establishing timing and combinational logic circuits in the same always block, the non-blocking assignment is used.

5) Do not use both a non-blocking assignment and a blocking assignment in the same always block.

6) Do not assign a value to the same variable in more than one always block.

7) Use the $strobe system task to display variable values with non-blocking assignments

8) Do not use #0 delay when assigning a value

Tips:1. Each signal within the always block must be defined as a register type;

Use of the 2.if else

if (expression 1) statement 1;

else if (expression 2) statement 2;

else if (expression 3) statement 3;

....

else statement N;

3. In each always block, there must be begin...end. Other branch statements, such as If...else,case, have more than one sentence to have begin...end.

The principle, design and Verilog realization of counter