The second stage of Self-writing processor (2) -- Introduction to OpenGL

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I will upload my new book "self-writing processor" (not published yet). Today is the sixth article. I try to write this article every Thursday.


2.3 introduction to OpenGL

The openmips processor implemented in this book is written using OpenGL. Therefore, the following sections in this chapter will introduce some basic knowledge about OpenGL, including syntax and structure. This is because this book is not a specialized book used to teach Verilog HDL, so the content introduced here is not the whole of it, but only some basic knowledge, and the knowledge used in the implementation of the openmips processor. If you want to learn more about the function of the function, you can refer to related books. There are many excellent books in this area. The author recommends "Digital System Design and OpenGL (version 4th)". In this chapter, we also refer to this book for the introduction of OpenGL.

Phil moorby, from GDA (gateway design automation), was the first in 1983. After that, moorby also designed the OpenGL-XL simulator, which was a great success, in this way, we can also promote the use of OpenGL. In 1989, Cadence acquired GDA. In 1990, Cadence publicly announced the release of OpenGL and set up an OVI (Open OpenGL International) organization to take charge of the development of OpenGL. Because of its concise, efficient, easy-to-use, and powerful functions, it is gradually accepted and favored by many designers. Its development has gone through several key nodes.

  • In 1995, Tilde-HDL became the IEEE Standard 1364-1995 (Verilog-1995 ).
  • In 2001, IEEE Standard 1364-2001 (Verilog-2001) was adopted, which expanded and enhanced the Verilog-1995 and modified some Syntax structures to make it easier to use.
  • In 2002, IEEE 1364 [1] was introduced to make the output of the synthesizer consistent with the results of simulation and analysis tools based on IEEE Standard 1364-2001. 1-standard, which defines a series of modeling criteria for RTL-level comprehensive use of HDL.
  • In 2005, Tilde HDL was updated again, that is, IEEE Standard 1364-2005 (Verilog-2005 ). This version is only a minor fix to the previous version. This version also includes a relatively independent new part, namely, the analog and mixed-signal ), this extension enables traditional OpenGL to model systems that integrate analog and hybrid signals.

Each of the following features is described in this section.

(1) Based on the C language, the C language is developed. In terms of syntax structure, the C language is inherited by many Syntax structures, and there are many similarities between the two.

(2) It is suitable for integrated circuit design and simulation of circuits and systems.

(3) can describe the designed system at multiple levels, from the Switch Level, the door level, the register transfer level (RTL) to the behavior level, at the same time, we do not impose any restrictions on the design scale.

(4) flexible and diverse circuit description styles, which can be behavior description or structure description. hybrid modeling is supported, each module in a design can be modeled and described at different design levels.

(5) Multiple built-in basic logic gates, such as and, or, and NAND, facilitate the description of the door-level structure; multiple built-in switch-level components, such as PMOS, NMOS, and CMOS, you can perform on-switch modeling.

(6) User-Defined primitive (UDP) Creation flexibility. The user-defined primitive can be either a combination logic or a time series logic. The descriptive capability of the Tilde HDL language can be further expanded through the programming language interface (PLI) mechanism.

2.4 structure of the module in OpenGL

The basic design unit of the OpenGL program is "module". A module has a specific structure, as shown in Figure 2-6. Each module consists of four main parts: module declaration, port definition, data type description, and logical function description.

The following is a 32-bit sub-device module. There are two input signals, in1 and in2. The result of adding the two signals is output through out.

Module add32 (in1, in2, out); // module declaration input in1, in2; // port definition, which is input port output out; // port definition, here is the output port wire [31: 0] in1, in2, out; // data type description, here is the wire-type assign out = in1 + in2; // logical function description endmodule

The following describes the basic structure of the module based on the examples of the sub-device.

1. Module Declaration

The module Declaration includes the module name and the list of input and output ports. The format is as follows.

Module name (Port 1, Port 2, Port 3 ......);

2. Port Definition

Specify the module port direction (input, output, bidirectional, etc.) in the following format.

Input Port 1, Port 2, Port 3 ......; // Input port output port 1, Port 2, Port 3 ......; // Output port inout Port 1, Port 2, Port 3 ......; // Bidirectional Port

3. Data Type description

All signals (including port signals and node signals) used in the module must be defined as data types. Each of the signal types is provided by using the following example. The specific meanings of each data type are described in Section 2.5.2.

Reg A; // defines the data type of signal a as reg-type wire [31: 0] out; // defines the data type of signal out as 32-bit wire.

For a port, you can put the data type description and port definition in one statement. Therefore, the above 32-bit calculator can be changed to the following form.

Module add32 (in1, in2, out); input wire [31: 0] in1, in2; // put the port definition and type description in one statement output wire [31: 0] out; assign out = in1 + in2; endmodule

For the port, you can also put the port definition and data type descriptions in the module declaration, instead of in the module. Therefore, the above 32-bit divider can also be changed to the following form, which is simpler.

// Put the port definition and data type description in the module declaration module add32 (input wire [31: 0] in1, input wire [31: 0] in2, output wire [31: 0] Out); assign out = in1 + in2; endmodule

4. Logical Function Description

The core part of the module is the logical function description. There are multiple methods to describe and define logical functions in the module. Several Basic methods are as follows, which will be detailed in section 2.6.

  • Define with assign continuous assignment statement
  • Define process blocks using always
  • Call components (also known as component examples)
2.5 base element 2.5.1 constant

There are three types of constants (constant) in OpenGL: integers, real numbers, and strings. Only Integer constants are used in the implementation of openmips. Therefore, only Integer constants are described here. The format is 2-7.

An example of some Integer constants is as follows.

8 'b11000101 // The binary number with an 8-bit width. The value is 11000101, which is equal to decimal 1978 'h8a // The hexadecimal number with an 8-bit width. The value is 8A, it is equal to decimal 1385 'o27 // The number of octal digits with a 5-bit width. The value is 27, which is equal to decimal 234 'd10 // the four-digit width decimal number. The value is 10.

If it is not explicitly indicated, the default value is decimal.

2.5.2 variable declaration and Data Type

The variable declaration format is 2-8. Only the data type and variable name are necessary, and other parts can be omitted. If the symbols and bits are omitted, the default value is set based on the data type. If the number of elements is omitted, the number of declared elements is 1 by default.

The data types can be net and variable.

1. Net Variables

Net is equivalent to various physical connections in the hardware circuit. It is characteristic that the output value changes with the input value. Net variables include multiple types, as shown in Table 2-1.

This book only uses the wire type when implementing the openmips processor. Wire is the most commonly used net type variable. Input and Output signals in the Tilde HDL module are set to wire type by default when the data type is not explicitly specified. A wire signal can be used as an input of any expression or an assign statement or an output of an instance component. For example, the 32-bit calculator in the previous article assigns a value to the out signal. For the synthesizer, the value of the wire variable can be 0, 1, x, and Z, where 0 indicates low level, logic 0; 1 indicates high level, logic 1; X indicates an uncertain or unknown logical state; Z indicates a high-impedance state. If no value is assigned, the default value is high-impedance Z.

2. Variable Variables

Variable variables are the data types that can save the data written last time. Generally, they correspond to a trigger, a lock, and other storage components on the hardware, but they are not absolute. When the synthesizer is integrated, it will be determined whether to map to a link or to a storage component based on its assigned value. Variable variables include multiple types, as shown in Table 2-2. This book only uses the reg type when implementing the openmips processor.

Variable variables must be assigned values in the process statement (initial or always. It will be described in section 2.6.

2.5.3 Vector

Figure 2-8 If the Bit Width in the variable declaration format is 1, the corresponding variable is a scalar. If it is not 1, the corresponding variable is a vector. The default value is a scalar. The bit width of a vector is defined in the following form.


The number on the left of the colon indicates the highest valid bit MSB (most significant bit) of the vector, and the number on the right of the colon indicates the lowest valid bit LSB (least significant bit) of the vector ). For example.

Wire [] bus; // 4-bit wire vector bus, where bus [3] is the highest bit, and bus [0] is the second-bit Reg [31: 5] Ra; // 27-bit reg-type vector Ra, where Ra [31] is the highest bit, and RA [5] is the regularized Reg [0: 7] RC; // 8-bit reg-type vector RC, RC [0] indicates the highest bit, while RC [7] indicates the lowest Bit.

There are two types of vectors: Vector class vector and scalar class vector, which can be distinguished by keywords, as shown below.

Wire vectored [] databus; // use the keyword vectored, which indicates the Vector class vector Reg scalared [31: 0] Rega; // use the keyword scalared, which indicates the scalar class Vector

If not explicitly stated, it is a scalar class vector by default. This book also only uses scalar class vectors. One or more adjacent bits can be selected for scalar class vectors, which are called bit-select) and select (Part-select ). For example.

A = Rega [6]; // bit Selection: assign one of the vector Rega to the variable AB = Rega []; // select the field, assign the 5th, 4, 3, and 2 bits of the vector Rega to variable B.

In the implementation process of openmips, memory is used and can be seen as a two-dimensional vector. The following is a memory definition, which defines a memory with a depth of 64 and a width of 32 bit for each element.

Reg [31: 0] mem [63: 0]; // mem is a 32-bit memory with a depth of 64.
2.5.4 Operators

The operators defined in OpenGL include Arithmetic Operators, logical operators, bitwise operators, Relational operators, equality operators, decimal operators, shift operators, conditional operators, and bitwise Concatenation Operators. For details, see table 2-3.


Most of the operations in Table 2-3 are well understood. I will not explain them in detail in this book.

(1) The difference between "=" and "=" in equality operators is: for the "=" operation, the two operands involved in the comparison must be equal by bit, the result is 1. If some values are in an undefined state X or a high-impedance state Z, the result is an undefined value x, it is required that the operands involved in the operation be the bitwise of the variable State X or the high-impedance state Z. The two operands must be completely consistent and the result is 1; otherwise, the result is 0. For example.

reg [4:0] a = 5'b11x01;reg [4:0] b = 5'b11x01;

For a and B above, "A = B" returns X, while "A = B" returns 1.

(2) The bitwise operator is the same as the bitwise operator number and logic algorithm, but the bitwise operator is a recursive operation of a single operand with, or, or different, it is placed before the operand and can subtract a vector into a scalar. For example.

Reg [3: 0] A; B = & A; // equivalent to B = (A [0] & A [1]) & A [2]) & A [3]

Bitwise operations require logical operations on the two operands by their corresponding bits, for example.

Wire [] A = 4'b0011; wire [] B = 4'b0101; then A & B = 4'b0001, A | B = 4'b0111

(3) Bit concatenation operator: Used to splice some bits of two or more signals. The format is as follows.

{Bit sequence 0, bit sequence 1 ,...... }

For example, the addition operation can be used together with the carry output.

Input [] Ina, INB; // addition input output [] sum; // addition and output cout; // carry assign {cout, sum} = ina + INB; // Concatenates the image with carry.

Bit concatenation can also be used to repeat some bits of signals. The format is as follows.

{Repeated times {Duplicated data }}

The above functions can be used to expand the symbol of the signal, for example.

// Extend the signed bits of data, s_data = {data [7], data [7], data [7], data [7], data} wire [] data; wire [11: 0] s_data; s_data ={{ 4 {data [7] }}, data };

(4) The operator priority is 2-9.












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