The SPI controller of cloud6410

 

* ****************************** Loongembedded ******* *************************

Author: loongembedded (Kandi)

Time: 2011.12.07

Category: Wince-driven development

* ****************************** Loongembedded ******* *************************

 

 

1. SPI Controller

1.1 Overview

The SPI bus is a full-duplex serial synchronous communication protocol. The serial peripheral interface of the SPI (serial peripheral interface) can support serial data transmission, it contains two independent 8/16/32 displacement register for sending and receiving respectively. During SPI transmission, data is synchronously sent (in serial mode) and received (in serial mode ).

 

1.2 The SPI Controller supports the following features:

1) full duplex, indicating that both sending and receiving can be performed.

2) The 8/16/32 displacement register for sending and receiving.

3) The 8-bit pre-division logic is determined by the low eight-Bit Clock configuration register.

4) three clock sources, including pclk, usbclk, and epll clock.

5) supports the Protocol of National semicondumicrowire and the serial peripheral interface of Motorola.

6) Two Independent sending and receiving FIFO, each 16 samples deep by 32-bits wide.

7) the master mode and slave mode are supported.

8) Only unsent operations are supported.

9) The maximum sending/receiving frequency is 50 MHz, but the maximum sending/receiving frequency is 20 MHz when cpha is set to 1.

 

1.3 signal description

There are four interfaces for the external signal between the SPI controller and the external device of the SPI interface of the SPI 6410. These interfaces can be used as general gpio ports when the SPI is disabled.

 

Xspiclk:

Serial clock signal, used to control the time of data transmission, can be used as input and output.

Xspimiso:

In master mode, the master device obtains data output from the output pin of the device through this pin, which serves as the input. In slave mode, the master device outputs data from this pin to the slave device, in this case, it is output.

Xspimosi:

In master mode, the master device outputs data to the slave device through this pin. In slave mode, the master device receives data from the device through this pin, as input.

Xspics:

From the selection signal, when this pin is low, all the data transmission/receiving order is executed.

 

1.4 SPI operations

One-bit serial data is transmitted between the SPI interface of and the peripherals. The SPI of supports sending or receiving FIFO data separately by CPU or DMA, and supports two-way data transmission at the same time. The SPI has two channels: TX channel and Rx channel. The TX channel has a way to transmit data from the Tx FIFO to peripherals, the RX channel receives data from peripherals to the rx fifo.

 

If the CPU or DMA needs to write data to the FIFO, the data must be written to the spi_tx_data register first, so that the content in this register will be automatically moved to the FIFO sending; to read data from the receiving FIFO, the CPU or DMA must access the spi_rx_data register. Then, the received FIFO data will be automatically moved to the spi_rx_data register. In combination with the shift register mentioned above, we will show the relationship between the data register, the FIFO and the shift register in Figure 1:

Figure 1 Relationship between data registers, FIFO, and shift registers

To better understand the control logic of SPI, the logic diagram of SPI bus protocol is attached, as shown in Figure 2:

Figure 2 SPI bus specification logical Diagram

 

1.4.1 Operation Mode

Hs_spi supports master and slave modes. In master mode, the master device generates hs_spiclk and sends it to peripherals. The xspics signal is used to select a slave device. When it is low, the data is valid, that is, xspics must be set to low before sending or receiving data packets.

 

1.4.2 FIFO access

The SPI of 8/16 supports CPU and DMA to access the first-in-first-out (FIFO) data. The size of the data accessed by the CPU and DMA can be/32 bits. If you select an 8-bit data size, the valid data bit range is 0 to 7. By triggering a defined threshold, the CPU can enable or disable FIFO access. The trigger threshold of each FIFO can be any value from 0 to 64 bytes. If DMA access is used, the txdmaon or rxdmaon bit of the spi_mode_cfg register must be set. DMA access only supports single transmission and 4 burst transmission. When sending data to the Tx FIFO, the DMA request signal remains high until the FIFO is full. In
When receiving data from the FIFO, the DMA request signal is high as long as the FIFO is not empty.

 

1.4.3 end byte in RX FIFO

In the interrupt mode, the number of samples in the rx fifo is smaller than the threshold value, or in the 4-burst mode of DMA, and no additional data is received. The remaining bytes are called the ending bytes. To remove these bytes from the rx fifo, the Internal timer and interrupt signal are required. Based on the APB bus clock, the internal clock value can be set to 1024 clocks. When the value of this timer changes to 0, the interrupt signal occurs and the CPU can remove these ending bytes from the rx fifo.

 

1.4.4 Data Packet Count Control

In master mode, SPI can control the number of packets received. To receive any number of data packets, you only need to set the packet_cnt_reg register. When the number of received data packets is the same as that set, SPI stops generating spiclk. If you want to re-load this function, A software or hardware reset is required, where software reset can clear all registers except special function registers, while hardware reset clears all registers.

 

1.4.5 chip selection Control

Xspics can be manually controlled or automatically controlled. For the manual control mode, auto_n_manual bit of cs_reg needs to be cleared from the selected signal control register. The xspics level of this mode is controlled by the nssout bit of this Register. For the automatic control mode, to determine the auto_n_manual position of cs_reg from the selected signal control register, the xspics level is automatically determined before the package and package, during which ncs_time_count value exists, in this mode, nssout is invalid. See:

Figure 3 waveform of automatic mode selection

1.4.6 SPI Transmission Format

In order to support peripheral devices with different transmission characteristics, the SPI of the initi6410 supports four data transmission formats, which are determined by cpol and cpha. The following describes the two concepts.

 

Cpol:

Cpol (clock polarity) Clock polarity control bit specifies that the serial clock is active high (that is, when the sclk clock is effective when it is high) or active low (that is, when the sclk clock is low when it is effective), this control bit has no significant impact on the transmission format. When cpol is set to 0, it indicates that sclk is low when it is idle; When cpol is set to 1, it indicates that sclk is high when it is idle.

 

Cpha:

The cpha (Clock Phase) Clock Phase Control bit selects one of two different basic transmission formats. cpha indicates the data sampling time, cpha = 0 if the data sampling time corresponds to the first hop variation edge of sclk, and cpha = 1 if the data sampling time corresponds to the second hop variation edge of sclk.

 

The Clock Phase and polarity of the SPI main device and the slave device should be consistent, so that the SPI main device needs to determine the cpol and cpha values based on the two characteristics of the clock phase and polarity of the slave device. In some cases, in order to allow communication between a master device and multiple slave devices with different requirements, the master device is required to change the Clock Phase and polarity.

 

Next, we will learn the transmission formats of cpha = 0 and cpha = 1 in the SPI bus specification.

Figure 4 sequence diagram of cpha = 0

1st hops:

The first hop of sclk, from the first data bit of the device to the master device (that is, the lock to the master device, the lock here can also be understood as sampling) and the first data bit of the master device. For some devices, as long as the device is selected, the first data output from the device data pin is valid. In this format, when the/SS pin is reduced, the first hop edge is generated for the half-cycle clock. In this case, the timing diagram of the SPI controller part cpol = 0 and cpha = 0.

Figure 5 waveform of cpol = 0 and cpha = 0

 

Next, describe the sequence diagram in Figure 4.

2nd hops:

The previous hop is locked from the serial data input pin to the LSB or MSB of the master device and the data bit of the slave device to the corresponding shift register, which is determined by the lsbfe bit.

 

In this way, the previous two hop edges complete the transmission of a Data bit. It also shows that the hop edges correspond to the same hop edges that are simultaneously sent and received, instead of sending a jump edge, the other jump edge is received.

 

3rd hops:

The next data of the SPI main device is from the output Pin Input to the input pin of the device, at the same time, from the next data of the device from the output Pin Input to the input pin of the main device, so cycle, in this process, the 16 hop edges of sclk are continued. The rule is as follows: when the hop edges are odd, the data is locked to the device, when the hop is an even number, the data is moved into the shift register.

 

In this way, after 16 sclk hops, the data in the SPI master device data register has been migrated to the slave device data register, previously, data from the device data register has been moved into the data register of the master device.

Figure 6 sequence diagram of cpha = 1

Some devices need the first sck hop edge before the first data bit output by the data output pin is valid. The data is synchronized to the master device and the slave device only when the second hop edge is valid, in this format, the first hop edge is generated by setting cpha bit (cpha = 1) at the beginning of the eight clock transmission operation cycles.

 

1st hops:

The first hop is generated immediately after the sck clock synchronization delay is half a cycle. The master device instructs the device to send its first data bit to the data input pin of the master device, however, this data bit is not a valid data bit of the data bytes to be sent. The sequence diagram of cpol = 0 and cpha = 1 of the SPI controller of is as follows:

Figure 7 sequence diagram of SPI controller cpol = 0 and cpha = 1

2nd hops

This is the hop direction between the master device and the slave device. That is to say, during the hop, the first data bit of the device is input to the master device (that is, the lock to the master device) and the first data bit of the master device.

 

3rd hops:

The previous hop is locked from the serial data input pin to the LSB or MSB of the master device and the data bit of the slave device to the corresponding shift register, which is determined by the lsbfe bit, this completes the transmission of a Data bit.

 

4th hops:

The next data of the SPI main device is from the output Pin Input to the input pin of the device, at the same time, from the next data of the device from the output Pin Input to the input pin of the main device, so cycle, in this process, the 16 hop edges of sclk are continued. The rule is as follows: when the hop edges are even, the data is locked to the device, when the hop is odd, the data is moved into the shift register.

 

In this way, after 16 sclk hops, the data in the SPI master device data register has been migrated to the slave device data register, previously, data from the device data register has been moved into the data register of the master device.

 

The following figure shows the waveform of the transmission format in 4 supported by the SPI controller of initi6410.

Figure 8 waveform 4 supported by SPI Controller