The story of "segment register" (mainly in the third segment)

I. Generation of segment registers

The generation of segment registers is due to the inconsistent width between the data bus and the address bus in the Intel 8086 CPU architecture.

The width of the data bus, that is, the width of the ALU (arithmetic logical unit). Generally, a CPU is "16-bit" or "32-bit. The data bus of the 8086cpu is 16 bits.

The address bus width does not have to be the same as the ALU width. Because the width of ALU is fixed, it was limited by the technology level at that time, at that time it could only create a 16-bit ALU; but the address bus is different, it can be designed wider. If the width of the address bus is the same as that of ALU, it is certainly a good solution. In this way, the CPU structure is balanced and addressing can be completed within a single instruction cycle, with the highest efficiency. In addition, from the perspective of software solutions, the length of a variable address can be expressed by an integer or a long integer.

However, the address bus width is also subject to requirements, because the address bus width determines the system addressable range, that is, the amount of memory that can be supported. If the address bus is too narrow, the addressable range will be small. If the address bus is designed to be 16 bits, the addressable space would be 2 ^ 16 = 64kb, which was considered insufficient at the time; intel eventually decided to set 8086 of the address space to 1 m, that is, 20-bit address bus.

If the address bus width is greater than the data bus, it may cause some trouble. Alu cannot compute the address data in a single instruction period. There are some feasible methods that are easy to come up with, such as defining a new register specifically for storing 4-bit high addresses, but this increases the complexity of computing, programmers need to multiply the assembly code to operate on address data and cannot maintain compatibility.

Intel has come up with a compromise: It segments the memory and designs four segment registers, Cs, DS, es, and SS, for instruction, data, other, and stack respectively. The memory is divided into many segments, each segment has a base address, of course, the base address is also a 20-Bit Memory Address. However, the segment register is still 16-bit. Its content represents the 16-bit height of the segment base address. The 16-bit address is followed by four zeros to form a 20-bit segment base address. The original 16-bit address is only the offset within the segment. In this way, a complete physical memory address is composed of two parts: the base address of the 16-bit segment and the offset of the 16-bit segment. Of course, the 12-bit address overlaps, these two parts are added together to form a complete physical address.

Base B15 ~ B12 B11 ~ B0
Offset o15 ~ O4 O3 ~ O0
Address A19 ~ A0

This addressing mode is also the "real address mode ". In 8086, the segment register is a pure 16-bit register, and the operation register instruction is not a privileged instruction. By setting the segment register and intra-segment offset, the program can access the entire physical memory without security.

In a word, the design of the segment register is a suitable option. Now it seems to be a temporary solution. The purpose of the design is to extend the address space from 64 KB to 1 MB, that's all. However, its addition has brought a lot of inconvenience to the future development of Intel series chips, and also brought troubles for understanding the i386 system.

Ii. implement protection mode

By the time 80386 came out, the technology had made great progress. 386 of ALU has jumped from 16 to 32, that is, 38086 is a 32-bit CPU, the structure is also relatively mature. Although the speed of the 80486 series to the Pentium series has increased by several orders of magnitude, there is no qualitative change, so it is collectively referred to as the i386 structure.

For a 32-bit CPU, as long as the address bus width is the same as the data bus width, it can address 2 ^ 32 = 4 GB memory space, which is enough, segment registers are no longer needed to help with expansion. However, intel cannot remove the segment register from the product because the new CPU is also a member of the product series. According to the compatibility requirements, the segment register must be retained.

At this time, the development of technology requires intel to implement the "protection mode" in its CPU, the user program's accessible memory range must be limited, and can no longer access all memory addresses. Intel decided to use segment registers to implement their protection mode, and built the protection mode on the basis of segment registers.

The description of a segment is not just a 20-bit starting address, but a completely new definition of the "segment description ". The structure of the description item is as follows:
B31 ~ B24 DES1 (4 Bit) l19 ~ L16
Des2 (8 bit) B23 ~ Blob
B15 ~ B0
L15 ~ L0

Each row is two bytes, a total of eight bytes, 64-bit.

DES1 and des2 are descriptions of the data segment, code segment, and read/write permissions. B0 ~ B31 is the base address of the segment, l0 ~ L19 is the segment length.

Note: The length of a specified segment is very necessary. If you do not limit the length of a segment, you cannot "protect" it. The access to a user program cannot exceed the segment range at least. In addition, the segment length is only 20 characters, which indicates the maximum length of 2 ^ 20 = 1 m, and the whole address space is 2 ^ 32 = 4 GB, is the segment length too short? In fact, in DES1, There is a unit used to indicate the length of a segment. When it is set to 1 (generally this is the case), it indicates that the length unit is 4 kb. In this way, the maximum possible size of a segment is 1 M * 4 k = 4G, which is consistent with the address space. 4 kb is the size of a memory page, indicating that the segment size is aligned to the page.

Also, have you noticed an interesting phenomenon? The Structure of the segment description item is designed to be discontinuous. Both the segment base address and segment length are divided into two sections. Such a design is related to the 80286 transition. The structure of the above segment description items removes the remaining three lines after the first line, which is the segment description item of 286. 286 is designed as a 24-bit address bus, so the base address of the section is 24 bits and the length of the corresponding section is 16 bits. After the address bus of 386 is extended to 32 bits, it must be compatible with the design of the 286 product, so we have to "patch" the segment description ".

In section 386, the segment register is still 16 bits. How can we store the segment descriptions of the 16 bits? Segment descriptions are no longer directly held by segment registers. Segment description items are stored in the memory, and the system can have many segment descriptions. These items are continuously stored to form a table, the 16-bit segment register only contains an index in this table, but it is not only a simple serial number, but also a data structure. The definition of this structure is as follows:

Index (B15 ~ B3) Ti (B2) RPL (b1 ~ B0)

Here, index is the index of the segment description table, which points to a segment description. RPL indicates the permission. 00 is the highest, and 11 is the lowest.

Another key issue is where the starting address of the segment description table in the memory is? Obviously, indexing alone is not enough. To this end, Intel has designed two new registers: GDTR (Global Descriptor Table register) and ldtr (Local Descriptor Table register), which are used respectively to store the address of the segment description table. The Ti bit in the segment register is used to indicate whether GDTR or ldtr is used.

When the user program requests access to the memory, the CPU determines which register to use based on the nature of the instruction, the address in the transfer instruction is in the code segment, and the address in the number instruction is in the data segment; locate the segment description item based on the index value in the segment register to obtain the base address of the segment. The address in the instruction is a intra-segment offset, Which is compared with the segment length to ensure that no cross-border is exceeded. Check the permission; add the base address and offset to form a physical address and obtain data.

In the new design, permissions and scopes are everywhere restricted. The user program can only access the authorized memory space, thus implementing the protection mechanism. In this way, Intel implements its own "protection mode" based on the segment register ".

3. coexistence with webpage Storage Management

The development of modern operating systems requires that CPUs support page-based storage management.

The page Storage Manager is separated from the Segment Storage Manager. There is no relationship between the two. However, for intel, it is also due to the historical reason of "segment register". It must establish the page type storage tube on the basis of the segment storage tube, although this is irrational from the design point of view and is not necessary at all.

In the Segment Storage tube, after the variable address sent by the program is mapped (segment base address + intra-segment offset), the obtained 32-bit address is a physical address, yes, it can be directly put into the address bus to get the number.

In the page storage, the process is similar. The variable address sent by the program is not the actual physical address, but a three-layer index structure, this address is mapped by a system to obtain the physical address.

Now, for Intel CPU, the above two ing processes must be performed one by one. The variable address sent by the program is called the "Logical Address". It is first converted into a "linear address" After segment ing, and then the linear address is used as the page ing input. Finally, the "physical address" is obtained ".

The Linux kernel implements page-based storage management, and does not become more complex due to the ing of Two-layer storage management. Linux focuses more on page-based memory management. For segment-based ing, It is simplified in a special way. Let each segment register point to the same segment description, that is, only one segment is set, the base address of this segment is 0, and the length of the segment is set to the maximum value of 4G, this segment coincides with the entire physical memory. After the logical address is mapped, it is the same as the linear address, so that the segment storage tube is "Transparent.

This is the story of "segment register" in Intel processor.