Thorough understanding of I/O architectures

Source: Internet
Author: User

To be able to work properly, a system must have a data paths mechanism, software and hardware systems are exception. For a computer system, there must be a data paths mechanism to ensure that the information data between the CPU, RAM, and I/O devices can flow correctly. These data paths, commonly referred to as buses, are the main communication channels inside the computer.

There is usually a system bus inside the computer to connect all the internal hardware devices. A typical system bus is the PCI ((Peripheral Component interconnect) bus. Other types of more-used buses are Isa,eisa, MCA, SCSI, and USB. A computer has several different types of buses, which are linked by bridges. There are two kinds of high-speed bus processing to reach or from the memory chip data transmission:

(1) Front-end bus: Connect CPU and RAM controller;

(2) Back-end bus: Connect CPU and external hardware device cache.

The host bridge (Hostbridge) connects the system bus and the front-end bus.

Data channels that connect I/O devices and CPUs can be collectively referred to as I/O buses. Peripherals are used to fit a peripheral bus, and most of the popular I/O buses are formed on personal computers. As can be seen, the type of bus affects the internal design of the I/O device and affects how the Linux kernel handles it.

The general purpose I/O architecture for PCs is as follows:

Next, I'll review the diagram in the order of the top down (i.e. I/O controller--> I/o Interface--->I/o Port) .

The device controller (I/O Controller) has the following two functions:

(1) Resolve the high-level commands received from the I/O interface and send the correct electrical signals to the I/O device, the I/O device according to these signals to perform the corresponding action.

(2) correctly parse and translate the electrical signals from the I/O device and modify the corresponding I/O status register values through I/OS interface. (I/O status registers are one of the I/O ports.) )

The I/O interface is a hardware circuit that is inserted between the I/O port and the corresponding device controller. It acts as an interpreter to parse the values in the I/O port into the command or data of the corresponding device. Accordingly, it also reads the status value of the device and updates the value in the I/O port.

There are two types of interface:

(1) Custom interface. Commonly used keyboard interface, graphics interface, disk interface, bus mouse interface, network interface and so on.

(2) Universal interface. Common serial port, and the port, PCMCIA (such as hard disk, network card, etc.) interface, SCSI interface, USB interface and so on.

For the sake of unification, the I/O port of the device is also structured as a series of dedicated registers:

(1) control register;

(2) Status register;

(3) input register;

(4) Output register.

As follows:

For the CPU, if it is to send data to a device, it is actually sent to the corresponding interface (I/O Interface), the interface circuit has a plurality of registers (also known as the port, "I/O port"), the access device is actually read and write these registers, all the information will be transferred to its device by the interface. In general, the CPU writes to the device control register as needed to execute the command, and reads the device's internal state from the device status register. The CPU will also fetch (Featch or pull) byte data from the input register, or write (push) byte data to the output register in a push way.

An external device that wants to connect to the system uses its own interface and a matching interface on the bus. There will usually be multiple peripherals, each peripheral interface circuit, there will be more than one port, each port needs an address, for them to identify a specific address value, is the system must solve the matter, at the same time, you also have a memory bar, may be 512M or 1G or greater Kingston, modern DDR2, etc. Each of their addresses also needs to be assigned an identity value, in addition, many peripherals have their own memory, buffer, like your memory bar, you also need to allocate memory for them ... Your CPU may need to deal with every byte of it, so don't expect to be lazy, and every inch of their land must be planned!

In order to plan the I/O port, there are two ways of addressing it: stand-alone addressing and unified addressing.

(1) Unified addressing:

The IO registers (i.e. IO ports) in the peripheral interface are regarded as the main memory cells, each end share population with a storage unit address, a portion of main memory is used as the IO address space, for example, in PDP-11, the highest 4K main memory as the IO device register address. The port occupies the memory address space, which reduces the storage capacity. Unified addressing is also referred to as "I/O memory", where the peripheral registers are in "memory space" (many peripherals have their own memory, buffers, peripheral registers and memory referred to as "I/O space").

(2) Independent addressing (separate addressing):

The IO address is separate from the storage address, and the i/0 port address does not occupy the address range of the storage space, so that there is another IO address unrelated to the storage address in the system, and the CPU must have an IO instruction (in, out, etc.) and control logic dedicated to the input/output operation. Stand-alone address, the address bus come up with a location, the device is not known to the IO port, or to the memory, so the processor through the MEMR/MEMW and Ior/iow two sets of control signals to achieve the I/O port and memory of different addressing. For example, the Intel 80x86 uses a separate address, CPU memory and I/O are addressed together, that is, the memory portion of the addresses and I/O addresses overlap. Stand-alone addressing is also known as an I/O port, and the peripheral registers are located in the I/O (address) space.

This article seeks to be easy to understand, the main reference book: Understanding the Linux Kernel

Thorough understanding of I/O architectures

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