Ti_dsp_srio-directio operation-LSU

The direct I/O (load/Store) module (that is, LSU) serves as the source of all outgoing direct I/O packets (LSU is used to configure the SRIo device that initiates data read/write, and the initiator sends the direct Io package ). with direct I/O, the rapidio packet contains the specific address where the data shoshould be stored or read in the destination device. direct I/O requires that a rapidio Source Device keep a local table of addresses for memory within the destination device. once t Hese tables are established, the rapidio source controller uses this data to compute the destination address and insert it into the packet header (insert the peer address to be accessed by the initiator into the header ). the rapidio destination peripheral extracts the destination address from the specified ed packet header and transfers the payload to memory via the DMA (the peer SRIo device extracts the destination address from the received packet header (that is, the sender wants the address of the access peer memory ), then the peer SRIo transmits the package payload to the destination address through DMA ). when a CPU Wants to send data from memory to an external processing element (PE) or read data from an external PE, it provides the Rio peripheral vital information about the transfer such asdsp memory address, target device ID, target destination address, packet priority, etc. essential, a means must exist to fill all the header fields of the rapidio packet. the load/store module provides a mechanisms to Han Dle this information exchange via a set of MMRs acting as transfer descriptors. these registers, shown in Figure 2-8, are addressable by the CPU through the configuration bus (CPU accessible, these registers are LSU registers ). there are 8 LSU in total. each LSU has its own set of 7-registers (there are eight LSU registers, that is, SRIo can transmit 8 Direct Io at the same time, each group of registers includes lsu_reg0 ~ 7 ). LSU_Reg0-4 is used to store "control" information (LSU_Reg0-4 contains information about user configuration, that is, control information), LSU_reg5-6 for "command" and status information (LSU_reg5-6 contains some status information, reflects the operating status of the LSU register ). all these registers are RW blocks t for lsu_reg6 which has a Ro and a wo view. upon completion of a write to lsun_reg5, a data transfer is initiated for either an nread, nwrite, nwrite_r, swrite, atomic, or maintenance rapidio transacti On (once the lsun_reg5 register is written, the SRIo hardware will actually start the work, including generating direct Io packets and sending packets. N indicates eight LSU register indexes). Some fields, such as the rapidio srctid/targettid field, are assigned by hardware and do not have a corresponding command register field.

Id size (2bit) in lsu_reg4 register ):

8b indicates that the SRIo device ID of the DSP is 8 bits, so that the SRIo system can support 2 ^ 8 SRIo devices.

The lsu_reg4 register can also configure the packet priority, the port from which the packet is transmitted, and the SRIo device ID of the target DSP.

Lsu_reg5 registers are used to configure the package type (operation type) and doorbell 16bit information.

The lsu_reg3 register is used to configure the number of bytes for transmission (which can be divided into multiple packets for transmission). The drbll_val bit indicates:

When drbll_val is equal to 1, it indicates that the 16bit doorbell information in lsu_reg5 is valid, and then the doorbell packet will be sent after the last packet is sent, the payload content of this package is the 16bit doorbell information in lsu_reg5 to notify (through interruption) that the data operation on the SRIo initiator end has been completed, and the peer end can be processed accordingly. In the figure, the FTYPE = 10 package is the doorbell package. The drbll_val bit here is only valid for non-Doorbell packages, such as nwrite packages. when data is written to the peer end through the nwrite operation (through the nwrite package) after completion, a doorbell package will be generated to notify the peer, so this bit can be configured when nwrite and other operations are configured.