SPI bus protocol and SPI timing diagram detailed 2014-02-20 21:41:28
Category: Embedded
The original URL SPI Bus protocol and SPI timing diagram detailedSPI, is the abbreviation of English serial Peripheral interface, as the name implies is the serial peripheral device interface. SPI, is a high-speed, full-duplex, synchronous communication bus, and on the chip's pin only occupies four lines, saving the chip pin, while the layout of the PCB space saving, convenient, it is for this simple and easy to use features, now more and more chips integrated this communication protocol.
SPI is a ring bus structure, composed of SS (CS), SCK, SDI, SDO, the timing is actually very simple, mainly under the control of SCK, two bidirectional shift registers for data exchange.
The rising edge is sent, the falling edge is received, and the high is sent first.
When the rising edge arrives, the level on the SDO will be sent to the register from the device.
When the falling edge arrives, the level on the SDI will be received in the main device's register.
Assuming that the host and slave are initialized ready: and the host's Sbuff=0xaa (10101010), slave sbuff=0x55 (01010101), the following will step through the data condition of the SPI 8 clock cycles (assuming the rising edge sends the data).
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Pulse host Sbuff slave sbuff SDI SDO
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0 00-0101010101 0 0
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1 0--10101
1 1--0 01010100101010110 1
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2 0--11010
2 1--0 101010010101011010
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3 0--10101
3 1--0 01010010 1010110101
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4 0--11010
4 1--0 101001010101101010
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5 0--10101
5 1--0 010010101011010101
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6 0--11010
6 1--0 100101010110101010
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7 0--10010101x 1101010101
7 1--0 001010101101010101
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8 0--1 0101010x 1010101010
8 1--0 01010101101010101 0
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This completes two registers 8-bit exchange, the above 0--1 represents the rising edge, 1--0 represents the falling edge, SDI, SDO relative to the host. According to the above analysis, a complete transmission period is 16 bits, that is, two bytes, because first the host to send commands in the past, and then from the machine based on the host's name to prepare the data, the host in the next 8-bit clock cycle to read the data back.
SPI Bus is Motorola's three-line synchronous interface, synchronous serial 3-wire mode of communication: A clock line sck, a data input line Mosi, a data output line miso; CPU and various peripheral devices for full-duplex, synchronous serial communication. SPI main features are: can send and receive serial data at the same time, can be used as a host or slave, provide frequency programmable clock, send end interrupt sign, write conflict protection, bus competition protection. The
SPI Bus has four modes of operation (SP0, SP1, SP2, SP3), the most widely used are SPI0 and SPI3.
SPI module for data exchange with peripherals, the output serial synchronization clock polarity and phase can be configured according to peripheral operating requirements, and the clock polarity (CPOL) has no significant impact on the transport protocol. If cpol=0, the idle state of the serial sync clock is low, and if cpol=1, the idle state of the serial sync clock is high. The clock phase (CPHA) can be configured to select one of two different transport protocols for data transfer. If cpha=0, the data is sampled on the first hop edge (up or down) of the serial sync clock, and if cpha=1, the second hop edge (up or down) of the serial synchronization clock is sampled. The SPI Master module communicates with the peripheral tone clock phase and polarity should be consistent.
SPI timing diagram detailed-SPI interface at the moment of output of the first bit of data in mode 0
SPI interface time to output the first bit of data in mode 0
The SPI interface has four different data transmission timings, depending on the combination of the two bits of Cpol and CPHL. The four timings are shown in Figure 1,
The relationship between time series and Cpol and CPHL can also be seen.
Figure 1
The Cpol is used to determine the level at which the SCK clock signal is idle, cpol=0, the idle level is low, cpol=1,
The idle level is high. Cpha is used to determine the sampling time, cpha=0, the first clock in each cycle along the sample,
Cpha=1, the second clock in each cycle is sampled along.
since I am using a device that works in mode 0 this timing (cpol=0,cpha=0), Figure 1 is simplified to Figure 2,
Focus on the timing of mode 0 only.
Figure 2
Let's focus on the first clock cycle of the sck, sampling data at the forefront of the clock (rising edge, first clock edge),
The output data on the back edge of the clock (falling edge, second clock along). First of all, the main device, the main device output (MOSI) outputs data bit1,
At the forefront of the clock is sampled from the device, and at what point does the main device output bit1? The output time of the bit1 is actually before the SCK signal is valid,
A half clock cycle is earlier than the rising edge of the sck. The output time of the bit1 is not related to the ssel signal. Then look at the slave device,
The input port of the main device miso is also in the forefront of the clock sampling from the device output of the bit1, that from the device and at what time output bit1 it.
The device is output bit1 immediately after the Ssel signal is valid, even though the sck signal is not yet functioning at this time. About the main device above
And the time from the device output bit1 bit, can be verified from Figure 3, 4.
Figure 3
Note in Figure 3, after the CS signal is valid (low level, note the situation after the decline of CS), deliberately using the delay program
Delay for a period of time, and then write to the data register to send the data to see the main device output bit1 (MOSI).
As can be seen, the bit1 (value 1) is the output at the time of the half-clock cycle before the SCK signal is valid (independent of the CS signal),
The rising edge of the first clock cycle of the sck is precisely sampled from the device.
Figure 4
In Figure 4, watch the CS and miso signals. We can see that after the CS signal is valid, the bit1 (value 1) is immediately output from the device.
Usually we do 16-bit SPI operations. Figure 5 Records the interface between the first byte and the second byte.
The last digit of the first byte is sampled on the rising edge of the sck, followed by the sck falling edge, and the first bit of the second byte is output from the device.
Introduction to SPI Bus Protocol (interface definition, transmission timing)
I. Technical performance The
SPI interface is Motorola's first full-duplex, three-wire synchronous serial Peripheral Interface with master-Slave architecture and support for multi-Slave mode applications, generally supporting only single-Master. The
clock is controlled by master, and in the clock shift pulse, the data is transmitted in bits, high in front, low in the rear (MSB first), and the SPI interface has 2 unidirectional data lines for full-duplex communication, with data rates up to a few Mbps in the current application.
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II, interface definition
SPI interface A total of 4 signal lines, are: Device selection line, clock line, serial output data cable, serial input data cable.
(1) MOSI: Main device data output, slave data input
(2) Miso: Master data input, slave data output
(3) SCLK: Clock signal generated by master device
(4)/SS: Slave enable signal, master device control
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Third, internal structure
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Four, transmission timing
The SPI interface in the internal hardware is actually two simple shift registers, the transmitted data is 8 bits, the main device generated from the device enable signal and the shift pulse, the bitwise transmission, high position in front, low post. As shown, the data changes on the falling edge of the SCLK, and the rising edge of a data is stored in the shift register.
The SPI interface does not have a specified flow control, and there is no response mechanism to confirm receipt of the data.
Timing (reprint)
