I. Family INSPECTION
1. Noun classification:
(1) Chip name: 2440,210,6410,
(2) Arm core: A8,ARM9,ARM11
(3) Instruction architecture: ARMV4,ARMV6,ARMV7
2. Each chip contains a core, and each type of kernel uses a specific instruction architecture. and arm Company is out ~ ~ ~ Sell Arm core. The most important thing in the chip is the arm core, which directly determines performance.
3. Nuclear historical evolution
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Cortex has three series:
(1) M-series, listed industrial area: No operating system, class single-chip microcomputer
(2) R series, real-time system: can run operating system
(3) A series, multimedia and Wireless communication: Performance and high
Their performance comparisons can be compared across the landscape
4. Chip comparison
2440 6410 210
(1) Processing speed: 400-500 533-667 800-1000
(2) Cache: 16kB 16kB (KB)
(3) Memory interface: SDRAM sdram/ddr DDR1/DDR2
(4) Support Os:wince/linux Wince/linux/andriod Wince/linux/andriod
(5) Other: Samsung discontinued normal production production
Two. Working mode
1. Big helper: Arm instruction manual
2. There are seven modes of operation to form different levels of use to prevent damage to the system. Different modes can access different registers and can run different instructions.
3.
(1) USR: mode (application) for normal application operation
(2) FIQ: Fast interrupt mode to handle fast case, high speed data transfer
(3) IRQ: External interrupt mode, normal interrupt processing
(4) SVC: Protected mode (management mode), privileged mode used by the operating system (kernel)
(5) ABT: Data access abort mode for virtual storage and storage protection
(6) und: Undefined instruction termination mode to support coprocessor with software emulation hardware
(7) SYS: System mode for running privileged-level operating system tasks (Armv4 or later)
4.USR is normal mode
The other six types are privileged mode
In addition to the USR and sys modes, five modes are abnormal mode
Three. Registers and addressing
1. Register Classification:
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2. Total 37 Registers, 31 universal registers, 6 status registers
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Where the registers of USR and sys are very similar
3. General-Purpose Registers:
(1) Non-packet register 0--7 (2) packet Register: 8--14
(3) PC pointer: R15
4 Status register: Only in abnormal mode, only the CPSR and SPSR,USR and SYS modes are only CPSR, in order to protect the scene
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(1) N: Represents a symbol, 1 indicates a negative number, and 0 indicates a positive number. such as two numbers for comparison and subtraction operations
(2) Z: When two numbers are equal, 1, otherwise 0, is also the comparison and addition operation of the majority (3) I: When he is 1, the processor cannot produce interrupts, that is, interrupt blocking
(4) F: Fast Interrupt shield, for 1 effective (5) M "4:0": indicates different working modes, readable and writable, and change the mode of operation, generally by reading, modification, writing to switch the mode of operation.
5. Special Registers
(1) R13:SP pointer, stack register (2) R14:LR link register. There are two special functions, each of which can be used to save the return address of the function, and also the return address after exception processing, such as interrupts.
(3) R15:PC pointer, program counter
6. Addressing method: The processor based on the information provided by the instructions to find the required number of operations, for the number of source operations
7. Immediate addressing: the operand is given directly, with # as the prefix
Add R0,r0, #0x3f
8. Register addressing: The operand is stored in the register, and the register appears directly in the instruction add R0,R1,R2
9. Register indirection: The operand is in memory, its corresponding address is stored in the register, and appears in the instruction as "register"
LDR R0,[R2]
10. Base Address Address: the operand in memory, and its corresponding addresses are based on the value in the base register, and then add the offset, so as to get the actual physical address of the operand in memory, in the form of "base register, offset" in the instructions Ldr R0,[R1, #4]
11. Relative addressing: Similar to the base address, except that the current PC pointer value as the base, and then add the label offset, so as to get the actual operand address, often used for the program's jump and return.
BL Next (relative addressing)
... next
... mov pc,lr
Topic 2-I look at arm from the inside